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jtd
- 本实验要完成任务就是设计一个简单的交通灯控制器,交通灯显示用实验箱的交通灯模块和七段码管中的任意两个来显示。系统时钟选择时钟模块的1KHz 时钟,黄灯闪烁时钟要求为2Hz,七段码管的时间显示为1Hz 脉冲,即每1s 中递减一次,在显示时间小于3 秒的时候,通车方向的黄灯以2Hz的频率闪烁。系统中用S1 按键进行复位。-To complete the tasks in this experiment is to design a simple traffic light controller, t
ask100
- 时钟同步模块:通过时钟同步模块,将模拟前端提取的时钟信号和数据进行同步,使得数字后端可以正确读取数据。-Clock synchronization module: The clock synchronization module, the analog front-end of the clock signal extraction and data synchronization, making the number of back-end data can be read correctly
593352pll
- 使用VHDL编写的数字PLL,对于想在FPGAzhong灵活使用时钟 的人有帮助。-Prepared by the use of VHDL digital PLL, the FPGAzhong would like flexibility in the use of the clock to help the people.
clock
- 基于VHDL的数字时钟的设计,能直接在开发板上看到运行结果-VHDL-based design of the digital clock can be seen directly in the development of on-board results
clock_skew_actel_2004
- this describes the clock skew problems and how to resove it by using various techniques in digital design and implementation
vhdl
- fpga的时钟讲解,vhdl的,源代码,可以测试-fpga on the clock, vhdl, and source code, to test
clk_en_gen
- 可靠的时钟产生器,采用同步设计,经过编译仿真,结果正确-Reliable clock generator, using synchronous design, compiled simulation, the results of the correct
alarm-clock
- 该代码用VHDL实现了闹钟的定时和提醒功能。里面包含四部分代码,分别实现了60,30,2分频;键盘控制;外围控制;用quartus2软件就可以打开,压缩包中附有四个代码的仿真结果。-The VHDL code used to achieve the alarm clock to remind the timing and function. Code which contains four parts, namely a frequency 60,30,2 keyboard control
DDSckkc
- 以把直接数字频率合成(DDS)看成这样一种技术,它能用数字值形式的信号控制正弦波的频率。最简单的DDS电路包括一个二进制计数器,一个以等间隔正弦波值进行全波编程的ROM,以及一个数模转换器,用于将存储的正弦波值转换为电压。计数器的时钟频率决定了正弦波的频率,但这 -To the Direct Digital Synthesis (DDS) as such a technology, it can use the digital value of the form of the frequen
deCPLDVHDLshijong
- 基于CPLD的VHDL语言数字钟(含秒表)设计 利用一块芯片完成除时钟源、按键、扬声器和显示器(数码管)之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短(设计过程中即可实现时序仿真)、调试方便、故障率低、修改升级容易等特点。 本设计采用自顶向下、混合输入方式(原理图输入—顶层文件连接和VHDL语言输入—各模块程序设计)实现数字钟的设计、下载和调试。 -CPLD based on the VHDL language di
Vhdl1
- Top Level VHDL Code -- simulate the relatively slow progress of an elevator car by dividing the -- clock down by an outrageously high number and scanning the car registers for -- an elevator s next -- (normally the signals used below wo
clock_divider
- This code contains the simple program that can be used for the clock divider to set any desireable clock from the master clock.
FPQ
- 基于FPGA的数控分频器,可以吧一个时钟信号分成不同频率的时钟信号。-FPGA-based digital frequency divider, a clock signal can now be divided into different frequency clock signals.
pll
- 一个实现任意倍频的,输入参考频率未知的pll,已综合实现-frequency multiple rely on dpll,unknown reference input clock
digital_clock_design
- 利用VHDL语言,逻辑器件设计CPLD,实现数字钟-Using VHDL language, design of logic devices CPLD, digital clock
shiyan10
- VHDL实用的时钟程序,已经通过实验,大家可以下载使用-VHDL Clock practical procedures are experimental, you can download to use
2
- FPGA设计中几个基本问题的分析及解决 多时钟系统,时钟设计,时钟歪斜,门控时钟,毛刺信号及其消除,FPGA中的延时设计,FPGA设计应注意的其它问题-FPGA design analysis of a few basic questions and solve multi-clock system, clock design, clock skew, clock gating, and the elimination of burr signal, FPGA design of the d
87361001Uart2
- VHDL语言编写的UART串口通讯,2400Hz的波特率时钟-VHDL language UART serial communication, 2400Hz clock of baud rate
ADC0809VHDL
- 8.4 ADC0809 VHDL控制程序 见随书所附光盘中文件:ADC0809VHDL程序与仿真。 --文件名:ADC0809.vhd --功能:基于VHDL语言,实现对ADC0809简单控制 --说明:ADC0809没有内部时钟,需外接10KHz~1290Hz的时钟信号,这里由FPGA的系 --统时钟(50MHz)经256分频得到clk1(195KHz)作为ADC0809转换工作时钟。 --最后修改日期:2004.3.20 -8.4 ADC0809 VHDL con
CLOK
- 时钟分频。使用原有高频信号,将其10倍频,得到可用于八段数码管显示的扫描信号-Clock frequency. The use of the original high-frequency signal, frequency-doubling of its 10, the eight can be used to display the scanned digital signal