搜索资源列表
Walsh
- 利用ISE编写的产生WALSH码的verilog程序,简单易懂,稍稍修改就可以产生出自己想的8 16 32 64位的WALSH码-Prepared using ISE verilog code generated WALSH procedures, easy to understand, a little modification can generate their own like the 8,16,32,64-bit code WALSH. .
CLOCK
- 文通过ALTERA公司的quartus II软件,用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为:计时功能,24小时制计时显示;通过七段数码管动态显示时间;校时设置功能,可分别设置时、分、秒;跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital
count_plus_last
- 对电机的编码器输入的正交编码信号进行4倍频处理 ,生成一个新的计数脉冲 ,同时判断电机的转动方向,输出一个方向标志电平信号,从而可以让DSP知道电机的转速和方向。-On the motor encoder inputs of the quadrature encoder signals 4 octave treatment, generates a new pulse count and at the same time to determine the direction of motor r
jiyu-FPGA-dianziqin
- 1) 主芯片:Altera 的FLEX10K20TC144-4 STC89C58RD+。 2) 要求扩展键盘接口电路,可以实现电子琴的一般功能,进行乐曲的手动演奏,此外还应该具有存储功能,可以将演奏的乐曲进行存储并在人工控制下进行回放。 3) 完成系统方案设计。 4) 编制相应的VHDL程序并进行相应的仿真工作,完成系统的调试工作。 5) 编写51系统程序,完成初始化、系统控制等功能。 6) 利用51系统实现系统的在线配置。 7) 发挥部分 可以进行乐曲的自动演奏。
LCD12864
- 利用FPGA在12864液晶屏上显示汉字。配置IO后可直接使用-Use of FPGA in the 12864 character LCD display. IO configuration can be used directly after
1chipmsx-cd
- VHDL实现的任天堂NES游戏系统,包含了CPU,APG,GPU等各个器件,可以下载到FPGA开发板上运行-VHDL implementation of the Nintendo NES game system includes a CPU, APG, GPU and other various devices, can be downloaded to the FPGA development board to run
VGA
- 压缩包中包含了用Verilog编写的视频控制模块,实现PAL制式到VGA制式的实时转换,同时包含了VGA专用ram配置模块,可直接实用-Compressed package includes the preparation of the video with the Verilog control module, PAL format to achieve real-time conversion to standard VGA, VGA also includes dedicated ram
wannianli
- 采用VHDL语言编写的万年历程序,可在液晶上显示!-Using VHDL language calendar procedures, can be displayed on the LCD!
music_1
- 这是一个在Quartus II软件中编写的vhdl程序。程序下载后可用蜂鸣器播放音乐 -This is a Quartus II software in the preparation of the VHDL program. After the buzzer can be used to download music player
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中,前9列为开销字节,它包含了很多重要的信息,本程序为SDH开销的接收处理,查找帧头,分频,勤务话字节E1异步fifo。可拆为三段源代码,不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
rs232
- fpga的串口读写程序,经硬件测试成功,波特率9600.可以改变分频值适应不同的时钟和波特率-fpga serial read and write procedures, by the hardware to test the success of 9600 baud rate. frequency value can be changed to adapt to a different clock and baud rate
uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b
xilnx_sata
- xilinx 的sata解决方案,已对其中内容作了修改,可实现综合-sata the xilinx solutions have been made to amend the contents of which can be used
FINALWORK
- 简易信号发生器 可产生正弦波、方波、三角波、锯齿波 周期可调 verilog-Simple signal generator can produce sine, square, triangle wave, sawtooth-cycle adjustable verilog
sine
- Verlog语言描述的正弦信号发生器的源代码可以方便的实现长生正弦信号-Language Verlog sinusoidal signal generator described in the source code can easily achieve the longevity of the sinusoidal signal
uart_EP3C16_FIFO
- Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
pro_4d1
- 此代码可实现8bits 108M 4路BT656 像素交织输入转为8bits 108M 4路行交织的视频数据,并有仿真文件,在modelsim中运行即可。-This code can be realized 8bits 108M 4 way BT656 pixel interleaving input into 8bits 108M 4 way line of cutting the video data, and there are simulation files can be run in
SPWM
- VHDL采用自然采样法写的SPWM,里面有正弦表,可以通过外接输入正弦波和三角波的频率。 -VHDL using written natural sampling SPWM, there are sine table, you can enter through the external sinusoidal and triangular wave frequency.
cic
- 五阶CIC梳状积分滤波器,可以综合,非常有参考价值-Fifth-order CIC points comb filter, can be integrated and very useful
DES_Verilog
- 这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test