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AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)
FPGA_clock
- 使用VHDL语言在FPGA上完成数字时钟设计，可作为设计的参考-In the digital clock on the FPGA design using VHDL can be used as a reference design
COUNT10
- 基于FPGA的一个带有异步复位和同步时钟使能的十进制加法计数器的设计，QuartusII编译通过，采用VHDL语言编写。-Based on FPGA with a reduction of asynchronous and synchronous clock can make the decimal additions counter design, QuartusII compile, USES the VHDL language.
mkjpeg.tar
- 用FPGA实现的JPEG编码器，可以直接使用，内含完成说明文档，经过验证无误。-• JPEG baseline encoding JPEG ITU-T T.81 | ISO/IEC 10918-1 • Standard JFIF header v 1.01 automatic generation • Color images only (3 components, RGB 24 or 16 bit, YUV input) • T
TUP3_clocckh
- 这是一个电子钟程序，采用VHDL开发发，在altera的FPGA板上实现。 -This is an electronic clock procedures, using VHDL development hair, altera FPGA board implementation.
9_TheBell
- FPGA，VHDL语言 蜂鸣器 响0.5S~~，时钟分频源程序，适用于所有FPGA芯片-FPGA, VHDL language buzzer 0.5S ~ ~, clock divider source, applicable to all FPGA chip! !
lcd12864
- fpga驱动lcd12864显示时钟，vhdl语言描述-the fpga drive lcd12864 display clock
8.4-ADC0809-
- 基于VHDL语言，实现对ADC0809简单控制,ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟信号，这里由FPGA的系 --统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。 -Based on VHDL ADC0809 simple control, ADC0809 no internal clock, an external clock signal of 10KHz ~ 1290Hz here by the Departm
64
- 利用FPGA实现的脉宽测试技术,基于VHDL,测试误差为时钟周期-FPGA implementation of pulse-width test clock cycle technology, based on VHDL, test error
1602lcdclock
- 使用vhdl语言在fpga平台上制作lcd电子钟，对于初学者，是一段很好的参考代码-Using VHDL language in fpga platform production LCD electronic clock, for beginners, is a very good reference code
8.4
- 功能：基于VHDL语言，实现对ADC0809简单控制 --说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟信号，这里由FPGA的系 --统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。 -: Based on the VHDL language, ADC0809 simple control- Descr iption: ADC0809 no internal clock, an external clock sign
digital-clock_VHDL
- 使用VHDL实现数字时钟，已在FPGA上验证-use VHDL to build a digital clock, has been validated on FPGA
uart_lcd
- 基于FPGA的UART通信，并用LCD(1602)显示通讯状态和通讯的数据。通过在ALTERA公司生产的DE2-115开发板上运行，证明此程序稳定可靠。时钟为50MHz，语言为VHDL,状态机。-FPGA-based UART communication, and LCD (1602) show the communication status and data communications. DE2-115 development board by ALTERA Company product
alarm
- 利用vhdl和verilog两种方式可以实现的fpga芯片的数字钟，其中包含多个可设计改动的个性化模块。源代码利用quartusii平台写作，可移植性很强。-Using vhdl and verilog fpga can be achieved in two ways-chip digital clock, which includes several design changes personality module. Source code using the platform quartu
digtal_clock
- FPGA实现数字钟VHDL语言编写,包涵整点报时，清零，调时调分等功能-FPGA digital clock VHDL language, includes the whole point timekeeping, cleared when the transfer function of adjusting grading
SIG_CLK
- 四分频，四个相位的时钟输出，FPGA，vhdl，xilinx-Divided by four, four-phase clock output, FPGA, vhdl, xilinx
TransfData
- 用于FPGA发送数据，采用VHDL语言编程，采用16位fifo发送，内涵时钟、复位、使能信号-FPGA is used to send data, using VHDL language programming, using 16 fifo sent connotation clock, reset, enable signal
UART_FPGA
- 此vhdl程序实现了在FPGA上构建UART通信串口。分为两部分，UART的发送端transfer和接收端receiver。需要外部根据需求提供波特率时钟。-This program implements the building vhdl UART serial interface on the FPGA. Divided into two parts, UART transfer sender and receiver receiver. Required to provide the ba
digital_clk
- VHDL Code for a digital bit clock counter and 7 segment display clock on a altera DE2 board with a cyclone II FPGA
RTC
- Implementation of Real Time Clock in VHDL coding. It can be implemented in XILINX305E FPGA kit.