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Digital-frequency-meter
- 这是应用VHDL语言在FPGA实现对频率进行分频的整个工程-This is the application of VHDL language in the FPGA implementation of the frequency divider of the whole project
filtro_hdlcoder
- Example project of a filter designed in MATLAB and exported to VHDL.
Final
- A "Tank Duel" game based on FPG, developmented in VHDL. -- Final Project in ASIC & FPGA Design class -A "Tank Duel" game based on FPG, developmented in VHDL.-- Final Project in ASIC & FPGA Design class
ads1282_code
- 用VHDL写的控制TI公司32位高精度ADC的程序，可以可靠运行，已经应用于实际项目-Control TI' s 32-bit precision ADC program written using VHDL, reliable operation, has been applied to the actual project
FPGA_Project
- To design fixed point to floating point encoder and experiment with simulation, synthesis and implementation features of the Xilinx Project navigator. Specifically, the objectives of this lab are: 1. To try out basic building blocks of VHDL beh
EDAmiaobiao
- 基于VHDL语言的EDA秒表作业设计，包括分频、秒表主体和数码管显示译码器，附有工程文件和管脚信息（EDA大作业西电02105143）-VHDL language based the EDA the stopwatch job design, including divide the stopwatch the main digital display decoder, with the project file and pin information (EDA Job Western Elec
DS18b20
- VHDL FPGA 温度传感器D18B20驱动程序 带工程文件 下载可以直接使用-VHDL FPGA temperature sensor D18B20 driver with a project file can be downloaded directly use
moveophone
- 移动式的游戏控制器基于vhdl. 简单结构 目前只能识别led-Due to the recent trend in creating devices that allow the playing of games using movement rather than a traditional joystick, controller, or keyboard, we felt that a project that followed this idea would be interestin
graphicallcd_latest.tar
- It s a project in VHDL for interfacing a graphical LCD with an FPGA. The project is an open-source file.
JTAG_CPLD_project_1.pdf
- JTAG_CPLD_project source VHDL code ，适用于开发JTAG接口。此工程使用Altera EPM570 MAX II CPLD，包含硬件和软件描述。-JTAG_CPLD_project source VHDL code, suitable for the development of the JTAG interface. This project using the Altera EPM570 MAX II CPLD, includes hardware a
SAR-ADC
- 这是一个用于实现逐次逼近型ADC的控制程序，用状态机实现的，用的VHDL语言。在实际项目中测试过-This is a successive approximation type ADC control program, written using the state machine tested in the actual project
VHDLproject-by-Qian-Yu
- 创建一个实时的视频处理器采用了FPGA技术的系统设计与VHDL。在这个项目中，我们实现滑动窗口滤波器，Sobel算子，一系列传感器和数字显示器VGA模块。-create a real-time video processor using FPGA technology in the course System Design with VHDL. In the project we implement modules for sliding window, sobel lter, a ran
SPI_Master_module
- 利用VHDL语言编写的SPI主机模块，采用内部自环回已经经过测试，发送接收数据正常，里面有modelsim工程，可以验证下仿真波形-SPI host module using VHDL language, has passed internal self-loopback test, sending and receiving data normally modelsim project, which can be verified under simulation waveforms
1freqdiv
- 使用VHDL代码高速而有效的实现了频率的分频，整个工程全部上传，bit文件可以直接下载-VHDL code fast and effective frequency divider, the whole project upload all bit file can be downloaded directly
NguyenAnHai_Project3_TLC
- it is project about VHDL to control trafict light.
myproj
- 使用vhdl语言设计波形发生器，产生正弦波，方波，三角波，锯齿波，实现频率，幅度可调。项目包附有设计说明和资料。-Waveform generator using vhdl language design, produce sine, square, triangle, ramp, realize the frequency, amplitude adjustable. Project package with design specifications and data.
reg8b
- 8位寄存器设计，用VHDL语言编写，用于DDS信号源中项目-8 registers design using VHDL language for DDS signal source project
adder16b
- 16位寄存器设计，用VHDL语言编写，用于DDS信号源中项目-16 registers design using VHDL language for DDS signal source project
digital-clock
- Project of digital clock made in vhdl code.
I2C_i2c
- fpga例程：用fpga实现i2c串口通讯的vhdl详细代码，完整的quartus工程，可直接用-fpga routines: i2c serial communication with fpga implementation details of vhdl code, complete quartus project, can be directly used