搜索资源列表
Memory
- 存储器类型介绍:SSRAM SDRAM Flash Memory EEPROM EPROM-Memory Introduction
Linux_bc
- 对vga接口做了详细的介绍,并且有一 ·三段式Verilog的IDE程序,但只有DMA ·电子密码锁,基于fpga实现,密码正 ·IIR、FIR、FFT各模块程序设计例程, ·基于逻辑工具的以太网开发,基于逻 ·自己写的一个测温元件(ds18b20)的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example(McGr ·这是CAN总线控制器的IP核,源码是由 ·FPGA设计的SDRAM控制器,有仿真代码 ·xili
DDRSDRAM
- DDR SDRAM的veilog hdl程序,经过验证 效果不错-DDR SDRAM' s veilog hdl procedures, good results verified
03.EDK8.2
- 使用xilinx virtex4芯片,设计环境为EDK,其中包含uart,片外sram操作,flash操作,DDR SDRAM操作,MAC自发自收,audio,video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-
Micron_DDR
- DDR2 SDRAM 颗粒初始化以及读写操作时序-Particles as well as the DDR2 SDRAM initialization timing to read and write operations
xilinx_sdcontroller
- xilinx公司的sdram控制器代码及说明文件-sdram controller of xilinx, codes and notes
SDRAMcontrollor
- SDRAM控制器,以下是我用VHDL编写SDRAM Controller的全部资料。文档提供的SDRAM控制器能工作在125MHz,我在实际工程中用到了120MHz,但没有再往上做测试了-SDRAM controller, the following is my SDRAM Controller using VHDL to prepare all the information. Documentation provided by SDRAM controller can work in the
webCam-FPGA
- 使用Verilog控制美光CMOS图像处理器,并转存到SDRAM中。使用FPGA为QL的带fuse系列-Control the use of Verilog Micron CMOS image processor and SDRAM in转存到. FPGA for use with QL series fuse
WRCTRL
- this VHDL Program get a 64 bit data and send it to a SDRAM-controller block to write into SDRAM and then get a 64bits data from SDR-block
Xil3SD1800A_MIG_simplifiedUI_vlog_v92
- verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
CAST_sdr_sdram_ctrl-xact
- Single Data Rate Mobile SDRAM Controller Core with AHB Interface
ddr_verilog_xilinx
- xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
SDRAM_design_source
- sdram的设计文档和参考源码。嵌入式开发中很难找到的源码。-sdram design documents and source code
mt48lc4m32b2.v
- SDRAM VHDL/Verilog simulation model
sdram_ver_134
- This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is based Xilinx FPGA Playform.
sdram_vhd_134
- This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
c_xapp851
- 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM (JEDEC DDR400 (PC3200) 标准)控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes
Sdram_Control_4Port
- 4 multi port sdram controller
ddr-sdram--chengxu
- ddr的控制程序,实用Verilog语言实现的非常的具体,非常无奈过的实用。-ddr
DDRSDRAM_VHDL
- 内附doc是DDR SDRAM 参考设计文档;model包含SDRAM VHDL的模型;simulation包含VHDL测试平台、modelsim工程文、设计 库函数;source包含vhdl源文件;synthesis包含工程的综合文件。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM VHDL model simulation with VHDL test benc