搜索资源列表
XilinxFree.lic
- 这是许可在Xilinx Vivado 2015利用免费的IP核生成(This is the license to utilize free IP core generation in Xilinx Vivado 2015)
project_1
- 在FPGA上实现一个流水灯,包括端口设定等(On FPGA to achieve a water led, including port settings)
project_2
- simple gates using ip integrator from xilinx
ps_ps_test
- 跑马灯,在vivado平台模拟,zybo开发板实现(Water lights, simulations in vivado platform, zybo development board implementation)
clock
- 一个简单的24h时钟,包含开机、关机、暂停、置数功能,以及整点时脉冲响五次(a simple digital clock implemented on Vivado)
Xilinx新一代FPGA设计套件Vivado配套资料
- verilog经典教程,入门者的必选书籍,非常实用,可以学习到很多的知识(verilog classic tutorial, entry must be books, very practical, you can learn a lot of knowledge)
temp
- 掌握时间一直是人们最基本的需求,而在快节奏的当今社会,时间更是一个很重要的工具。电子时钟是利用电子技术构成时钟功能的装置,与机械式时钟相比具有更高的准确性和直观性,且无机械装置,拥有更长的寿命,因此现在越来越得到广泛的使用。按照系统设计功能的要求,系统分为综合计时模块,数据调整模块,红外接收解码模块以及显示模块等4个模块,其中综合计时模块又包含7个子模块(年、月、日、星期、时、分、秒),每个子模块都具有预置,计数和进位的功能。(Time is always the basic need of p
prova_ped
- project for test in PED currently going through the course
FS4LPWPIXGFMOS1
- uart transmitter using verilog.checked in vivado 16.2 version
1_FM_Radio
- 基于vivado与MATLAB联合仿真,实现FM立体声广播,通过simulink的仿真以及Dps平台的帮助,可以直接下板运行(simulation basing on vivadao and matlab)
Sdram
- 在vivado中调用SDRAM的IP核,并通过数据的读入,读出,验证IP核的使用,文件中有仿真结果时序图。(In the vivado call SDRAM IP core, and read through the data, read, verify the use of IP kernel, the file has simulation results sequence diagram.)
Comprehensive_FM_IP
- 在vivado平台上的用verilog语言编写的FM直接调制程序(On vivado platform of FM modulation directly program written in verilog language)
Mealy_TrafficLight
- 基于FPGA交通控制器的Mealy状态机实现(Mealy state machine controller based on FPGA traffic)
random
- 用简单的线性反馈移位寄存器实现了伪随机数的生成…(The pseudo random number is generated by a simple linear feedback shift register)
MEM_Array
- vivado HLS中自定义axi4接口的实现(Implementation of custom axi4 interface in vivado HLS)
CRC
- 4G-LTE标准中turbo编码所用到的CRC编码,绝对可用!(CRC encoding turbo encoding used in 4G-LTE standard)
axi_dma
- 在zedboard开发板上采用vivado通过AXI进行DMA数据传输(Using vivado to transfer DMA data through AXI on zedboard development board)
scripts
- 低通滤波器的实现,通过不同的切割方式实现后,生成的vivado文件资源的使用情况不同,对其进行分析(The implementation of the low pass filter, after the implementation of different cutting methods, the use of the generated vivado file resources is different, to analyze it.)
lab5
- 串口控制器,基于vivado软件下开发,包含代码及管脚分配文件(Serial port controller)
uart_test
- VIVADO uart测试程序基本调试通过 希望有用(VIVADO uart test program)