搜索资源列表
wp416-Vivado-Design-Suite
- XILINX VIVADO综合编译工具操作和说明-XILINX VIVADO
Xilinx
- XILINX大讲堂、十招加速Vivado IPI设计、Vivado HLS 中指针作为top 函数参数的处理、Vivado HLS 中的浮点设计编码风格与技巧、编写高效Vivado HLS 工程testbench 的三个要素-XILINX auditorium, ten strokes accelerate Vivado IPI design, Vivado HLS deal with top pointer as function parameters, Vivado HLS floating
Vivado_debug_to_MATLAB_doc
- 介绍了Xilinx Vivado debug调试环境下，将调试数据导入MATLAB的方法，简单易用，欢迎交流-Guide for Xilinx Vivado debug, import data to matlab.
ug902-vivado-high-level-synthesis
- Xilinx Vivado HLS 高层次综合工具的用户手册-User manual for Vivado HLS Xilinx high level synthesis tools
DDR3_ip
- 本文档开发环境为vivado软件，描述了ddr3 IP core的生成过程，亲测可行。-this document describe ddr3 ip core genetator process.I test it by myself.
随处可见的知识
- vivado使用，xilinx软件的使用，编程注意问题
IP
- 如何快速在Vivado IPI中使用HLS生成的IP-How to fast in IPI IP using HLS generated Vivado
vivado HLS开发教程
- 官方文档，与vivado HLS开发相关，介绍了HLS的特点和作用，即如何通过高级语言如C生成硬件描述语言，并生成IP核，方便FPGA开发。并给出了一些具体例程。
vivado_jian_ming_jiao_cheng_
- Vivado中文使用教程,详细介绍了XILIN开发工具vivado的使用方法.-Vivado Chinese design manual
license
- LICENSE FOR VIVADO , please try, very good I think
AXI-54
- this all about viviado AXI four light bus communication. it is good for every one who is intersted in studying vivado axi light interfacing-this is all about viviado AXI four light bus communication. it is good for every one who is intersted in study
Assignment-02-1
- this all about viviado AXI four light bus communication. it is good for every one who is intersted in studying vivado axi light interfacing-this is all about viviado AXI four light bus communication. it is good for every one who is intersted in study
ug897-vivado-sysgen-user
- FPGA和matlab关联用到的文档，很有帮助，大家可以学习一下(FPGA and matlab associated with the document, very helpful, we can learn about it)
using of Vivado
- Vivado安装、生成bit文件及烧录FPGA的简要流程以及亲测可用vivado 2017.1 license。(the license of vivado2017.1)
guide of Vivado 2014
- 《Xilinx FPGA权威设计指南 Vivado 2014集成开发环境》(A good guide of FPGA with vivado 2014.)
04_led_test
- Verilog写的led灯，可用Vivado/ISE仿真平台仿真(Progress is not created by contented people.)
vivado常用综合属性
- vivado常用综合属性，可以帮助对设计进行约束(vivado commonly used attributes, can help to design constraints)
at7_ex02
- 8个拨码开关分别控制8个LED的亮灭状态。基于vivado平台编写的Verilog代码(8 dial switches control 8 LED's bright and dead state respectively. Verilog code based on vivado platform)
Vivado入门教程
- 本文讲述了Xilinx FPGA编程软件Vivado的使用入门，包含新建工程，仿真等内容，适合完全没有接触过Vivado的新手使用
ug947-vivado-partial-reconfiguration-tutorial
- PGA动态重构技术正适应了这种要求，用有限的资源去实现更大规模的逻辑设计，大大提高了资源利用率。但它决不仅仅是一种新型功能电路的应用，其涉及数字系统设计方法、设计思想的变革，可以使数字系统单片化的设计从追求逻辑规模转向追求逻辑的分时复用；从专用的固定功能逻辑系统转向功能可自适应进化的逻辑系统。动态重构技术是未来FPGA研究和使用方向