搜索资源列表
lab1_flash_led.xpr
- Verilog语言编写led流水灯,vivado环境编写-led water lights written by verilog
VGA
- FPGA verilog写的关于vGA的显示程序，使用vivado编程环境-FPGA verilog written on the vGA display program, the use of vivado programming environment
digital_clock
- 基于vivado的FPGA数字闹钟的程序，verilog语言编写-Vivado based on the FPGA digital alarm clock procedures, verilog language
fft_ex1
- 基于verilog的FFT设计，使用vivado作为开发平台-Verilog based on the FFT design, the use of vivado as a development platform
license
- LICENSE FOR VIVADO , please try, very good I think
fifo_control
- vivado project file for fifo in vhdl
shift_reg_control
- vivado project for shift register in vhdl
interpolation
- vivado project file for down scaling of image by scale factor 2
AXI-54
- this all about viviado AXI four light bus communication. it is good for every one who is intersted in studying vivado axi light interfacing-this is all about viviado AXI four light bus communication. it is good for every one who is intersted in study
Assignment-02-1
- this all about viviado AXI four light bus communication. it is good for every one who is intersted in studying vivado axi light interfacing-this is all about viviado AXI four light bus communication. it is good for every one who is intersted in study
S02_CH03_EMIO
- 基于ｖｉｖａｄｏ的ＥＭＩＯ流水灯的实现，可以直接运行-Based on vivado EMIO water lamp implementation, you can run directly
S02_CH02_MIO
- 基于ｖｉｖａｄｏ的ＭＩＯ点灯的实现，可以直接运行-Based on vivado MIO lighting implementation, you can run directly
S02_CH05_UBOOT
- 利于ｖｉｖａｄｏ的ｓｄｋ环境实现ｕｂｏｏｔ的编译-Conducive to vivado sdk environment uboot compiler
tiaozhi
- 基于verilog HDL的数字正交解调FPGA实现，仿真结果验证正确，IDE为vivado 2014- U57FA u4E8Everilog HDL u7684 u6570 u5B57 u6B63 u4EA4 u89E3 u8C03 u5B9E u73B0 uFF0C u4EFF u771F u7ED3 u679C u9A8C u8BC1 u6B3 u786E uFF0CIDE u4E3Avivado 2014
jietiao
- 基于verilog HDL的数字正交（调制）FPGA实现，仿真结果验证正确。vivado 2014- U57FA u4E8Everilog HDL u7684 u6570 u5B57 u6B63 u4EA4 uFF08 u8C03 u5236 uFF09FPGA u5B9E u73B0 uFF0C u4EFF u771F u7ED3 u679C u9A8C u8BC1 u6B63 u786E u3002vivado 2014
Freq_gen
- VHDL语音写的标准分频模块，在vivado开发环境下运行-VHDL voice write standard frequency module, run in vivado development environment
rs232
- 基于RS232的串口传输程序，开发环境为vivado-RS232-based serial transmission procedures, the development environment for vivado
Watch
- FPGA开发板的简易时钟源码，开发环境为vivado-FPGA development board of the simple clock source, the development environment for vivado
GPIO_PS_MIO
- VIVADO 2016.4 通过PS和PL实现GPIO接口的实现方式（1），这是完整工程！-VIVADO 2016.4 u901A u8FC7PS u548CPL u5B9E u73B0GPIO u63A5 u53E3 u7684 u5B9E u73B0 u65B9 u5F0F uFF081 uFF09 uFF0C u8FD9 u662F u5B8C u6574 u5DE5 u7A0B uFF01
GPIO_PS_EMIO
- VIVADO 2016.4 通过PS和PL实现GPIO接口的实现方式（2），这是完整工程.-VIVADO 2016.4 u901A u8FC7PS u548CPL u5B9E u73B0GPIO u63A5 u53E3 u7684 u5B9E u73B0 u65B9 u5F0F uFF082 uFF09 uFF0C u8FD9 u662F u5B8C u6574 u5DE5 u7A0B.