搜索资源列表
GPIO_PL_IPCORE
- VIVADO 2016.4 通过PS和PL实现GPIO接口的实现方式（3），这是完整工程！-VIVADO 2016.4 u901A u8FC7PS u548CP u5B4E u73B0GPIO u63A5 u53E3 u7684 u5B9E u73B0 u65B9 u5F0F uFF083 uFF09 uFF0C u8FD9 u662F u5B8C u6574 u5DE5 u7A0B uFF01
I2C_slaver_verison3.0
- I2C从机模块，包含testbench，平台是vivado,仿真测试通过。(I2C slave module, including testbench, the platform is vivado, simulation test passed.)
简易数字钟
- 基于basys3的简易数字钟，可用于vivado开发环境入门，功能有计时和显示模块。(Basys3 based simple digital clock, vivado development environment can be used for entry, function, timing and display module.)
code.sources
- 秒表代码加上相应的key，测试通过可以直接用于vivado(zcscscsasfsdfsfasfasf)
vivado-boards-master
- 弟弟顶顶顶顶顶我的顶顶顶顶顶顶顶顶顶顶顶顶顶顶顶(dadawdafefrgrgsrfsfsefegweg)
mcu_led2
- 基于vivado平台，使用microblaze搭建一个小系统，并能点亮led(Based on the vivado platform, the use of MicroBlaze to build a small system, and can light LED)
MCPU
- 多周期CPU的verilog代码，用vivado可以仿真出波形(multi-cycle CPU by verilog and using vivado to simulate.)
led_test
- 实现流水灯的控制verilog程序，源程序vivado 2015.4(Achieve water light control, Verilog procedures)
mult88
- 两个8*8矩阵相乘，每个矩阵内部元素相同，简化运算；modelsim编译仿真，ise或vivado下载，实现FPGA显示。(Two 8*8 matrix multiplication, each element of the same matrix, simplifying the operation; Modelsim compiler simulation, ISE or vivado download, to achieve FPGA display.)
lab1
- Verilog lab1 is used for learning vivado
gate_test
- 使用vivado hls 对GATE代码进行封装，主要调试stream接口(using vivado hls to archieve GATE syn, to debug the AXI4-stream interface)
LAB2
- zynq上实现流水灯的软硬件协同设计，利用vivado 2015.2版本eda软件开发。(Zynq realizes the design of hardware and software of water lamp, and uses vivado version 2015.2 EDA software to develop it.)
PUB
- 使用xlilnx的vivado为基础环境开发的示波器，采用串口屏显示图像(Using xlilnx vivado based environment development oscilloscope, using serial display images)
ps_bram
- 通过ZYNQ的PS部分读写片上BRAM存储器(Read and write on-chip BRAM memory via the PS portion of the ZYNQ)
mem_wr
- 通过ZYNQ的PS部分读写DDR3存储器(Read and write the DDR3 memory via the PS portion of the ZYNQ)
DigitalFrequencyMeter
- 使用Basys3开发板，采用等精度测频方法实现信号的测频并通过LCD1602显示。(The use of Basys3 development board, the use of equal precision frequency measurement method to achieve signal frequency measurement, and through the LCD1602 display.)
sim_Xilinx综合与仿真设计指导
- Xilinx自己出的仿真设计指导，使用vivado工具必备参考资料。(The Synthesis and Simulation Design Guide provides a general overview of designing Field Programmable Gate Array devices using a Hardware Descr iption language. It includes design hints for the novice HDL user, as w
src
- 用于国密4的加解密算法实现，采用verilog 语言，可进行vivado仿真，vivado版本是2013，结果经测试正常，适合从事相关行业的工作人员进行借鉴和开发。(The code is realized and simulated by verilog. The simulation result has been confirmed by the author. It is recommended to download by the researchers who are in the
ug897-vivado-sysgen-user
- FPGA和matlab关联用到的文档，很有帮助，大家可以学习一下(FPGA and matlab associated with the document, very helpful, we can learn about it)
hf_mot
- 电机驱动及编码器同步采样，内部兼具多重滤波采样处理算法。(Motor drive and encoder synchronous sampling, the internal multi filter sampling and processing algorithm.)