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ethernet 10-100 monitoring
- this is using mac IP core for ethernet connection in ISE xilinx for ethernet 10/100
ddr3_rw_ctrl
- verilog基于DDR3 xilinx IP核 的DDR3的读写控制，方便学习(it is based on DDR3 IP core of xilinx)
axi_ipif_v2.3
- The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point
黑金Sparten6开发板Microblaze教程V1.0
- 黑金xilinx fpga MB软核教程(Black gold Xilinx FPGA MB soft core tutorial)
pll_test
- PLL，即锁相环。是FPGA中的重要资源。由于一个复杂的FPGA系统往往需要多个不同频率，相位的时钟信号。所以，一个FPGA芯片中PLL的数量是衡量FPGA芯片能力的重要指标。FPGA的设计中，时钟系统的FPGA高速的设计极其重要，一个低抖动, 低延迟的系统时钟会增加FPGA设计的成功率。本例程调用Xilinx提供的PLL核来产生不同频率的时钟, 并把其中的一个时钟输出到FPGA外部IO上, 也就是开发板的SMA接口上。(PLL, pll. It's an important resource
xilinx_lib.tar
- 用于modelsim仿真的xilinxfpga平台IP库，以ise 13.x为基础制作，在modelsim10下验证通过。(xilinx IP core library for modelsim simulate, based on ise 13.x, verified in modelsim10.)
help_lib
- 1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core man
microblaze_GPIO
- 基于xilinx 的软核microblaze的GPIO IP核程序(GPIO IPcore program for soft core MicroBlaze based on Xilinx)
10_rom_test
- 讲解赛灵思Spartant_6系列FPGA的ROM IP核的调试过程，供大家参考学习(Explain Xilinx Spartant_6 Series FPGA ROM IP core debugging process, for your reference learning)
Embedded-MP3-Player-master
- 利用XILINX FPGA 嵌入式核编写的C语言程序(C language program written in XILINX FPGA embedded core)
try
- 利用xilinx公司开发的vivado平台中的IP核-加法器，实现加法(The addition of IP core adder to the vivado platform developed by Xilinx is applied.)
test
- 利用xilinx公司开发的vivado平台中的IP核-rom，实现存储(Using IP core -rom in vivado platform developed by Xilinx, storage is implemented.)
demo
- 利用xilinx公司开发的vivado平台，实现调用romIP核的功能(Using the vivado platform developed by Xilinx, the function of calling romIP core is implemented.)