搜索资源列表
FPGA-Train
- FPGA基础培训，包括： FPGA基本架构 Xilinx工具流程 实验1：Xilinx工具流程演示 实验2：架构向导和PACE 实验3：全局时序约束 实验4：合成技术 实验5：CORE Generator系统 实验6：利用ChipScope-PRO-Basic FPGA Architecture Xilinx Tool Flow Lab 1: Xilinx Tool Flow Demo Architecture Wizard and PACE L
TCOLLOR_CHAR_h
- 此ip核是xvga视频接口控制器，，主要针对xilinx公司的开发工具 -This IP core is the xvga video interface controller, the main development tool for xilinx
jpeg_hardware.tar
- 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V
EtherCAT_IPCore_Xilinl
- EtherCAT从站控制器芯片ET1817及其IP_Core应用-EtherCAT Slave Controller IP Core for Xilinx FPGAs
EDK_Interrupt
- 基于Xilinx的EDK工具编写的中断服务程序，可以实现硬件设计IP核之间的相互调用。-Based on the EDK Xilinx written tool interrupt service routine, can realize the hardware design IP core the interaction between the calls.
Xedk_for_busyI
- XILINX 出品 EDK快速学习资料。 EDK在 Xilinx FPGA上构架一个CPU软核， 以提高整个系统的灵活性，和可扩展性。 -XILINX produced the EDK rapid learning materials. EDK Xilinx FPGA architecture of a CPU soft core in order to improve overall system flexibility, and scalability.
blk_mem_gen_ds512
- Xilinx Block Memory Generator IP Core
MicroBlaze
- Xilinx 推出的软核微处理器__Microblaze-Xilinx introduced the soft-core microprocessor
phase_test
- VHDL,简易音频数字相位表的设计与实现 数字相位测量仪在工业领域中经常用到的一般测量工具，主要应用与同频率正弦信号间的相位差的测量显示。 本系统采用FPGA实现测量的核心部分，主要由数字鉴相、累加计数器、控制器以及寄存与显示译码电路组成。该系统硬件电路简单，整个系统采用硬件描述语言VHDL作为系统内部硬件结构的描述手段，在XILINX公司的ISE9.1的软件支持下完成。可以对20Hz~20kHz频率范围内的音频信号进行采样鉴相处理，并将数据传回FPGA进行相位差计数累加、测量运算，最后送显
ps2
- 在赛灵思的spartan—3E开发板上实现键盘输入开发板显示的核心代码，使用EDK设计-Keyboard input development board core code, use the EDK design in Xilinx spartan-3E development board
lab4
- 使用赛灵思的EDK、SDK开发环境编写的微处理器内核，包括整个工程所需要的全部源代码。-Microprocessor core using the Xilinx EDK, SDK development environment written, all the source code needed to include the entire project.
verilog
- it is xilinx SDR SDRAM controller core
xcn12014
- xilinx how to use core generator
fir_compiler_ds534
- 详细的描述了XILINX ISE软件里的IP核的内部结构。详细的介绍了滤波器的各个内部机构和各个功能。-A detailed descr iption of the internal structure of the the XILINX ISE software IP core. Detailed introduction of various internal organs and the various functions of the filter.
Xilinx_FPGA_FFT_Application_Note
- Xilinx FPGA中FFT IP核的使用笔记，内部有FFT硬核的端口说明和具体设置以及源代码，对于数字信号处理研究人员，能图像处理、雷达成像、实时通信开发人员较多的开发时间！-Xilinx FPGA in the FFT IP core using a laptop internal hard core of the FFT port descr iption and specific settings as well as the source code for digital signa
test_myip
- xilinx EDK virtex II xc2vp30 用户自定义IP核led灯实验-the xilinx EDK virtex II xc2vp30 user-defined IP core led light experiment
ISEPrj
- Xilinx Zynq的PS+PL使用，用PS添加IP核，然后从IP核添加GPIO，并与板上LED相连，实现led的逻辑。注意不能使用helloworld模板。-For the Xilinx Zynq PS+ PL, PS Add IP core, and then add GPIO IP core and connected to the on-board LED, led logic
axiethernet_v3_00_a
- xilinx fpga软核mac控制器的调试源码，可以在linux下编译也可在xilinx的sdk中编译-xilinx fpga mac controller soft-core debugging source code can be compiled under linux can also be compiled in a xilinx sdk
uartps_v1_03_a
- zedboard开发板硬核串口调试源码， 可以在linux下编译也可在xilinx的sdk中编译-zedboard hard core development board serial debugging source code can be compiled under linux can also compile the xilinx sdk
Four_MB_FSL
- 基于Xilinx Microblaze的四核嵌入式系统设计源码-embedded system design based on xilinx Microblaze core