搜索资源列表
SRAM
- 使用Verilog语言编写的SRAM读写程序,不用添加IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-SRAM using Verilog language literacy program, do not add the IP core in Xilinx Spartan-6 run through, is a very good program Verlog
brom_16x8
- 使用Verilog语言编写的ROM读写程序,使用IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-ROM using Verilog language literacy program, the use of IP core in Xilinx Spartan-6 run through, is a very good program Verlog
fft_test3
- matlab simulinc file for calculating xilinx fft core using system generator
osd_driver
- Xilinx FPGA的视频处理IP核 OSD的驱动程序，很好用！-Xilinx FPGA video processing IP core OSD driver, very good!
IP-Release-Notes-Guide
- 该文件包含xilinx 公司发布的所有IP CORE的介绍，比较全面。-This file contains all the company released xilinx IP CORE presentation, more comprehensive.
srio_test_1
- xilinx rapidio仿真,xilinx ip core 改核为收费核，用liscense获取核文件，共享个大家学习-xilinx rapidio
dac904_lock
- 采用xilinx的FPGA的DCM IP核进行开发的DA程序。-Using the xilinx FPGA-DCM IP core for the development of DA procedures.
v6Integrated-Block-for-PCIE-UG
- 赛灵思官方公布的PCIE集成端点核设计用户指导，是FPGA从业者的好帮手-Xilinx Integrated Endpoint official PCIE core design user guide, is a good helper for FPGA practitioners
xfft_v3_2_pipe_64
- vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband-vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband
FIFO
- 这是一个在xilinx下运行的关于FIFO的IP核设计的程序。-This is a run on the FIFO xilinx IP core design process.
lut
- 可参数化配置的CAM模块，仿照xilinx IP core设计而成，使用SRL16E基本单元实现，节省空间-Can be parameterized configurable CAM module, modeled xilinx IP core designed, implemented using the basic unit SRL16E, space-saving
CONVERT
- This scr iptconvert a image to coef values for ip core block ram generator xilinx
LogiCORE-IP-Video-Scaler-v4.0
- The Xilinx Video Scaler LogiCORE™ IP is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis.
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
ug586_7Series_MIS-xi
- 有关于xilinx平台DDR3 ip core介绍-xilinx ip core
Xilinx_PCIe_Core-DMA
- 本文档介绍了一种基于Xilinx Endpoint Block Plus PCIe IP Core，由板卡主动发起的DMA设计。该设计利用通用的LocalLink 接口，所以方便的兼容支持Xilinx PCIe 硬核的器件，例如Virtex 5，Virtex 6，Spartan 6，并且实际在ML555 和ML605 开发板上实际测试通过。此外，驱动将板卡的控制封装起来，提供用户层简单的读写接口，方便上层程序的开发。-This document describes an approach bas
dds
- dds xilinx ip core for using
aurora_bram
- Xilinx SP605评估板 Aurora IP(GTP 简单协议) 核功能验证 调试源代码 chipscope验证通过-Xilinx SP605 Evaluation Kit Aurora IP core functional verification debugging source code and chipscope verified
Xilinx_DDR
- 本文档对ISE开发环境利用MIG调用DDR2 IP CORE进行了进行了详细的介绍，对初学者很有帮助。其中FPGA芯片为Xilinx公司SP6 FPGA, DDR2 内存为Micron 公司的一款 R2 MT47H128M8 芯片。-This document calls ISE development environment using MIG DDR2 IP CORE conducted a detailed descr iption, very helpful for beginners.
hash_function_sha3
- The synthesis software is Xilinx ISE version 14.4. The low throughput core has been synthesized targeting a very cheap Spartan 3 (XC3S5000-4FG900). This project is licensed under the Apache License, version 2. I prefered on the internet