搜索资源列表
lcd.ucf
- the lcd ucf file in xilinx ise
VIRTEX2-ISE-VHDL
- XILINX virtex5 板子上做演化硬件时ISE 12.1中的硬件构架语言描述-XILINX virtex5 VHDL
zhongzhilvbo
- xilinx ise 与modesim联合验证中值滤波 含verilog源程序和整个工程文件-the xilinx ise modesim median filter containing joint verification verilog source, and the entire project file
fir_compiler_ds534
- 详细的描述了XILINX ISE软件里的IP核的内部结构。详细的介绍了滤波器的各个内部机构和各个功能。-A detailed descr iption of the internal structure of the the XILINX ISE software IP core. Detailed introduction of various internal organs and the various functions of the filter.
vga1
- 基于赛灵思的ISE实现的VGA驱动模块，仿真通过-Based on the Xilinx ISE realized VGA driver module, through simulation
isen
- 基于FPGA设计工具Xilinx ISE 编写的程序代码 包含有计数器，状态转移码，交通灯，时序约束等程序-Program code written based on FPGA design tools Xilinx ISE includes procedures such as counters, state transition code, traffic lights, timing constraints
lic_Xilinx_ISE_Vivado
- 这是Xilinx ISE 14.X以及vivado、vivado_hls的license，亲测可用-Xilinx ISE 14.x vivado, vivado_hls license, pro-test available
step
- 步进电机控制的FPGA代码，包括方向控制模块、激磁方式选择模块、定位模块以及输出脉冲。在Xilinx ISE 14.2环境下仿真验证过。-FPGA code stepper motor control, including directional control the module excitation mode selection module, positioning module, and the output pulse.
clk_div3
- 自己用xilinx ise编写的分频器程序，可以奇分频偶分频，分频系数可以自己设置。方便产生各种时钟信号-Divider program prepared using the Xilinx ISE, odd even divide divider division factor can set up their own. And convenient produce a variety of clock signal
wave_generator
- 文件里包括了利用xilinx ISE 设计波形发生器所要用到的三角波，正弦波，矩形波rom文件-File including the use of the Xilinx ISE design waveform generator to use the triangle wave, sine wave, square wave rom file
LED_TEST
- Verilog的LED闪烁程序，xilinx ISE开发环境-Verilog LED flashes, Xilinx ISE development environment
BlazeNoC_QoS-master
- BlazeNoC_QoS：支持QoS的可重配置片上网络路由，有很高的性能。此代码包括完整的Xilinx ISE的工程，可以很方便地修改和移植。-BlazeNoC_QoS: QoS-reconfigurable chip network routing, a high performance. This code includes a complete Xilinx ISE project, can be easily modified and transplantation.
I2C
- iic协议 用verilog hdl语言，可以在xilinx ise软件 编译 综合-iic agreement verilog hdl language can be compiled in xilinx ise software integrated
verilog-hdl
- 很少有完整介绍ISE环境下FPGA开发的资料，这是在Xilinx ISE开发平台下进行FPGA设计比较好的教程，感觉挺不错的-there is few full descr iption ISE FPGA development environment information, which is in the Xilinx ISE development platform for FPGA design is a good tutorial, I feel pretty good
irig_b
- 用来实现IRIG_B码的解码程序，在XILINX ISE上运行过没有问题，-Used to achieve IRIG_B code decoding process, in XILINX ISE run-off is no problem,
1602LCD
- 1602LCD原理,介绍基于xilinx公司的软件ISE制作LCD灯显示的原理介绍-LCD xilinx ISE
proj1
- 在Xilinx的ISE下用VHDL实现的3-8线译码器。-In the Xilinx ISE implementation using VHDL 3-8 line decoder.
multi_cpu
- 用xilinx ISE 14.3开发的多周期CPU系统，开发语言为verilog HDL.仿真调试与实际测试均已通过-Using xilinx ISE 14.3 development of multi-cycle CPU system, development language for verilog HDL. Simulation debugging and practical tests have passed
xilinxusb
- Xilinx usb下载电缆的图纸资料，可直接制版，然后下载Xilinx的ISE软件进行固件升级。制作图纸准确，使用与官方的下载电缆完全一致。-Xilinx usb download cable drawings, direct plate, and then download the Xilinx ISE software for firmware upgrades. Produce accurate drawings, using the official download cable ex
VHDL_design
- 本综合实验包括节拍脉冲发生器、键盘扫描显示和八位二进制计数器三个模块。采用VHDL语言为硬件描述语言，Xilinx ISE 10.1作为开发平台，所开发的程序通过调试运行验证，初步实现了设计目标。-This includes comprehensive experimental beats pulse generator, display and keyboard scan eight binary counter three modules. Using VHDL as the hardwar