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3Channel_CIS_Processor_with-VHDL.ZIP
- This usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by
jj
- 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采
lab5
- m*n的ram，包含m*n个ram，使用VHDL编译，可在xilinx里面运行-m* n the ram, contains m* n a ram, using the VHDL compiler, which can be run in xilinx
new_bord_TX_10bitX2_2_5G
- Xilinx VirtexII-pro 的开发板工程文件，它是在ISE开发环境中实现的。连接有RAM、串口、LED灯、Camera-link接口等，实现的从工业相机到光缆的转换。-xilinx virtex2-pro project,camera-link
ygyTest
- 利用开源网站上的8051核，在Spartan 3A开发板上实现成功，开发环境是Xilinx ISE Design Suite 12.3，顶层文件基于原理图开发，扩展了外部ROM和RAM，且更改了地址宽度-implment the mc8051 IP in spartan-3A FPGA starten kit.
C51
- mc8051在xilinx nexys3上的移植，包括ROM和RAM-mc8051 xilinx nexys3
Package
- Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 11
jpeg_hardware.tar
- 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V
bram_16x8_top
- 使用Verilog语言编写的RAM程序,可以双向读写,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-RAM using Verilog language program, you can bi-literacy, in the Xilinx Spartan-6 run through, is a very good program Verlog
CONVERT
- This scr iptconvert a image to coef values for ip core block ram generator xilinx
monitoringV5
- 文件的FPGA是基于Xilinx ISE写的，所用开发板为zedboard7020 484系列，完成的功能为：读取XADC里的温度，VCC，并存储到RAM中，通过流水灯实现翻看，读取等功能.-Document is based on Xilinx ISE FPGA wrote, the use of development board for zedboard7020 484 series, completed functions: reading XADC in temperature, VC
lab5
- 用Xilinx内核生成器系统生成DCM内核 和存储器内核（ROM、RAM)等-DCM core and memory cores generated by Xilinx CORE Generator System (ROM, RAM), etc.
bram
- Xilinx FPGA内部RAM的使用实验-Xilinx FPGA internal RAM usage experiments
ram_4_4
- this is a 2 bit ram for xilinx whit ise 9.2
HWL_ASYNC_FIFO_DRAM_BA
- asynchronous fifo based on distributed RAM. xilinx fpga. VErilog language.
microblaze实例教程
- 一般而言，Xilinx Microblaze会被用来在系统中做一些控制类和简单接口的辅助性工作，比如运行IIC、SPI、UART之类的低速接口驱动，对FPGA逻辑功能模块初始化配置及做些辅助计算等等。类程序的代码量普遍不大，常常在十几KB到几时KB之间，因此对存储的需求通常也不是太高，使用FPGA内部RAM资源便已经够用(Generally speaking, Xilinx Microblaze will be used to do some auxiliary work of control