搜索资源列表
verilog-HDL-learning
- 从零开始学verilog HDL ，包括Altera实验板原理图，xilinx实验板原理图和一些实验源程序-From scratch learn verilog HDL, including Altera experimental board schematic, xilinx test board schematics and source code of some experiments
jtag-Verilog
- JTAG verilog code for xilinx fpga
UART
- xilinx官网提供的VHDL,UART串行通信模块，肯定好用，官方提供-xilinx official website provides VHDL, UART, FPGA communication module is certainly easy to use, official
FPGACPLDXilinx-ISE-5.X--verilog
- FPGACPLD设计工具Xilinx ISE 5.X使用详解》配套光盘-FPGACPLDXilinx ISE 5.0--verilog
Verilog-HDL-Design
- FPGA入门的，云创工作室很好地一本书，主要以XILINX公司的芯片为主!-A very good book from Yunchuang studio for FPGA newer,and this book mainly talks about the verilog HDL and the XILINX FPGA!
dma(including-driver).xapp1052
- xilinx 官方dma 的verilog实现，包含windows和linux驱动。-XILINX s dma design of verilog ,including windows driver and linux driver .
Manchester-Encoding-Verilog
- THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR
MP3-design-using-verilog
- 基于Xilinx XUPV2P平台(FPGA开发板)的MP3播放器设计-MP3 player design based on the the Xilinx XUPV2P platform (FPGA development board)
verilog
- it is xilinx SDR SDRAM controller core
verilog-hdl
- 很少有完整介绍ISE环境下FPGA开发的资料，这是在Xilinx ISE开发平台下进行FPGA设计比较好的教程，感觉挺不错的-there is few full descr iption ISE FPGA development environment information, which is in the Xilinx ISE development platform for FPGA design is a good tutorial, I feel pretty good
flipflop_d
- Xilinx Verilog D触发器 绝对好用-Xilinx Verilog D flip-flop is absolutely easy
FT_LUT6_L
- Verilog of XILINX LUT6 of Xilinx-Verilog of XILINX LUT6 of Xilinx
XILINX DDR2
- xilinx ddr2 ip核的verilog例子
verilog coding
- verilog coding EE 517, homework2, using xilinx
MUSIC
- verilog实现xilinx的音乐播放（使用蜂鸣器）-xilinx verilog realize music player (with buzzer)
UART-Verilog-source
- Verilog编写UART串口例程，实现FPGA与上位机串口通信，利用ASCII码进行大小写转换，在Xilinx Virtex-5开发板测试通过-UART serial routines written in Verilog, FPGA serial communication with the host computer using the ASCII code case conversion, in the Xilinx Virtex-5 development board test
Random-number-generator-verilog
- Verilog code for a pseudo random number generator using linear shift registers. Implemented on Basys2 with Xilinx. Project report also is included.
Xilinx
- 使用Xilinx的FPGA开发教程，Xilinx平台主要支持VHDL和Verilog的编程和实现。-Using Xilinx FPGA development tutorial, Xilinx platform is mainly supported by the programming and implementation of VHDL and Verilog.
sp605PCIe
- xilinx评估板sp605的PCIe的verilog源程序(已经经过调试)-Evaluation Kit for PCIe-sp605 xilinx verilog source (which has been commissioning)
module-song2
- xilinx VERILOG fpga BASYS2 音乐单次播放实现-xilinx VERILOG fpga BASYS2 music single player to achieve