搜索资源列表
ADDER
- 本设计是用32位的并行全加器的,可以实现浮点运算!-The design is a parallel 32-bit full adder, and floating-point operations can be achieved!
full_add
- 这是一个全加器，有三个输入，有两个输出，输入分别是两个加数，一个进位，输出分别是和，进位-This is a full adder, three input, two output, input is represented by two summand, a binary output, respectively and, binary
fulladder4
- VHDL图形文件实现的4位全加器，希望对大家有用！-VHDL graphics files to achieve four full adder, in the hope that useful!
FAdder
- 全加器的设计，实现二进制的加法，一个输出为进位，一个输出为计算值。
PLD
- vhdl语言实现cpld功能，本程序包括全加器，触发器，交通灯程序，适用maxII软件调试。-include full_adder,plus,traffic
half_adder
- 一个半加器，具有进位和位数相加的基本功能，可作为全加器的基本模块-One and a half adder with binary and the sum of the basic functions of the median, full adder can be used as the basic module
f_adder8
- fpga八位全加器(vhdl语言),由画图法制作,将八个一位全加器(由一位半加器组成)组合制成-fpga eight full adder (vhdl language)
f_adder_4bit
- 四位二进制全加器，用原理图输入的形式实现，在Quartus II 5.1下编译通过。-4 binary full adder, with schematic input in the form of implementation, compiled in the Quartus II 5.1 adoption.
FullAdd
- 全加器结构描述是从设计实体的内部结构对结构体进行描述的，并给出该实体所包含的模块或元件的相互连接关系-fulladd
Full_adder
- 一种学习用的小程序，主要用与VHDL仿真的全加器的一段代码！大家可以下载进行修改于仿写-A learning to use a small program, mainly used with the VHDL simulation of a full-adder code! You can download the modified Yu Fang Xie
fulladder
- 本代码实现了全加器的功能，可供初学者学习-This code implements a full adder functions, for beginners to learn
chap7
- 几十个经典程序，结构描述的4 位级连全加器，1 位全加器，用条件运算符描述的4 选1 MUX-Dozens of classic procedure, the structure described in the four-level with full-adder, a full-adder, using the conditional operator described in the four selected 1 MUX, etc.
AdderE
- synplify中tcl语言应用，使用AdderE八位全加器为例，介绍一个设计针对不同器件综合-synplify in the tcl language application, use AdderE eight full-adder as an example, an integrated design for different devices
vhdl
- vhdl半加半减及全加器的实现即功能具体代码的编写-vhdl half-Canadian half-and full-adder function of the realization that the preparation of a specific code
f_adder
- 一位加法全加器，可以实现低位进位输入和高位进位输出。-full adder
f_adder
- 用VHDL语言写的全加器，比较简单-Written in VHDL language with the full-adder
cpu
- 用全加器设计8位运算器逻辑电路图 2、根据逻辑电路用 VHDL编程实现 3、调试编译通过后，仿真 -this file can help you learn the design of cpu
EDA
- 课程实验，VHDL语言实现半加器全加器，频率计等，共四个-eda
for_ws
- 裡頭有加法器,全加器,rippple adder-full adder ,rippple adder
Adder4
- 源码，内容是用VHDL语言编写的四位全加器-Source code, using VHDL language of the four full-adder