搜索资源列表
music1
- VHDL 多功能数字钟源码音乐模块2，自扒简谱-Multi-function digital clock source VHDL music module 2, since the expense of musical notation
shuzizhong
- 这个是关于用VHDL语言设计出来数字钟的程序，能够实现最基本的功能，对于想学习VHDL语言的人来说，是一个很好练习的例子。-This is about the design using VHDL, digital clock out of the program, to achieve the most basic functions, for people who want to learn VHDL language, it is a good practice example.
clock1
- 本程序用VHDL编写数字钟，具有定点报时，手动调整时间等功能，能下载到板子上显示时间。-This program written by VHDL digital clock, with a fixed broadcast, manually adjust the time and other functions, can be downloaded to display the time on the board.
clock
- VHDL编程--数字钟 非常适合初学者-VHDL Programming- digital clock is ideal for beginners
clock
- 在FPGA下用VHDL语言设计的数字钟程序-Under the FPGA design using VHDL, digital clock program
shizhong
- vhdl描述的数字钟，功能一样，方法不同-vhdl descr iption of the digital clock, the same function, different methods
8952
- 这是一个基于VHDL语言的数字钟设计,它是EDA的一个实例-This is a program for clock ,it is a example for EDA.
clock
- 用VHDL 语言设计数字钟，实现在数码管上显示分钟和秒，并且可以手动调节分钟， 实现分钟的增或者减。该设计包括以下几个部分： （1）分频电路的设计，产生1Hz 的时钟信号，作为秒计时脉冲； （2）手动调节电路，包括“时增”“时减”“分增”“分减”。 （3）时分秒计时电路。 （4）7 段数码管显示电路。-Design with VHDL, digital clock, to achieve in the digital display minutes and seconds,
clock
- 用VHDL实现多功能数字钟 闹铃 计时 动显 报时等-VHDL realization of multi-functional digital clock with alarm timer was timekeeping and other fixed
sy6
- 数字钟的VHDL源程序，里面附有数字钟的VHDL源程序和原理图的数字钟电路，数字钟有en,clk,clr等接口。-Digital clock in the VHDL source code, which the VHDL source code with a digital clock and schematic of the digital clock circuit digital clock with en, clk, clr and other interfaces.
eclock
- 数字钟 分模块设计 实现基础功能 VHDL编写 -eclock vhdl
FPGAVHDLeclock
- 数字钟设计报告 包括源码 仿真 设计原理等 vhdl编写 -vhdl fpga eclock
vhdlclock
- 数字钟的实现，包括报时，校时，清零，闹钟等功能，内附源文件电路图跟源代码。-This is a digital clock to achieve the VHDL. Using eight digital tube display!- Adjustable alarm can be school.
Counter60sec
- VHDL语言编写的一个六十进制计数器(用于秒)，一个脉冲输入引脚，一个复位引脚，8个BCD码输出引脚，一个进位输出引脚。与我的其它8个模块配套构成一个数字钟。 -A 60 binary counter（for second） programmed with VHDL language.A pulse input, a reset input, eight BCD code output. It is one of my total 9 modules that are used to de
Debounce
- VHDL编写。在CPLK开发板上设计的数字钟的去抖动电路。该模块相对独立，是学习去抖动的好资料。该模块跟我其它的8个模块配套构成一个数字钟。-Programmed with VHDL.A debouncing circuit which is part of a digital clock designed on a CPLD development board.The module is independent from others and is useful for learning de
Displayer
- VHDL编写的针对八段数码管的显示译码电路。实现动态扫描输出小时、分钟和秒。是基于CPLD开发板设计的一个数字钟的一部分。-Programmed with VHDL.The decoding and displaying circuit for 8-segments displayer.It outputs the data of hour,minute and second in order with dynamic scaning method.It is one of my total 9
Distributer
- VHDL编写的分频器。用于将50MHz的时钟脉冲分频成一个500Hz的扫描时钟和1Hz的秒脉冲。与我的其它8个模块配套构成一个数字钟。-Programmed with VHDL.A clock distributer which generates a 500Hz scaning clock and a 1Hz second impulse. It is one of my total 9 modules that are used to design a digital clock.
FlashTime
- 用VHDL编写。称为校时闪烁电路。一般的电子表在校时时都会使被校正的时间不停地闪烁。此模块实现了类似的功能。与我的其它8个模块配套构成一个数字钟。 -Programmed with VHDL. It is called a flashing circuit(when time is being revised).Generally, a digital watch will flash the currently revised time(for example,hour) to let t
RvsTime
- 用VHDL编写。数字钟校时电路，根据表示是否校时的输入引脚、是校正小时还是校正分钟的输入引脚决定校正状态。接受一个按钮的脉冲输入，每输入一个脉冲，被校正的时间增加1.与我的其它8个模块配套构成一个数字钟。-Programmed with VHDL.The time-revising circuit of a digital clock. Detect the inputs and decide if revise time, hour or minute. It recepts an impul
ADigCLK
- 用VHDL编写的一个数字钟。该模块是顶层模块，用VHDL例化语句例化各个子模块并组装成一个完整的数字钟。与我的其它8个模块配套构成一个数字钟。 -A digital clock programmed with VHDL.This module is the top-level module, it utilizes the Component instantiation of VHDL to incorporate all submodules into a complete digital