搜索资源列表
基于FPGA的直接数字频率合成器(DDS)设计
- 基于FPGA的直接数字频率合成器(DDS)设计 (源程序),FPGA-based direct digital synthesizer (DDS) design (source code)
DDS.rar
- 实现函数波形发生器的功能,内有用自己编的源代码实现的,也有用quartus的IP核实现的。,The realization of the function waveform generator function, useful for their own realization of the source code, it also uses the IP core quartus achieved.
cordicDDS
- Cordic算法实现DDS的Verilog 源码,14位精度,非常实用的。-DDS algorithm Cordic the Verilog source code, 14-bit accuracy, very practical.
FPGA-DDS
- 在FPGA内,以查表方式实现频率直接合成器(DDS)功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
singnal
- VHDL实现通用通信信号源,包括sin,cos,方波,三角波,BPSK,GMSK,ASK,16QAM等信号的产生以及DDS,PLL的VHDL系统代码-VHDL implementation of universal communication sources, including sin, cos, square, triangle, BPSK, GMSK, ASK, 16QAM and other signal generation and DDS, PLL system, the VHDL
200741691252
- dds源代码,vhdl程序,函数信号发生器。-dds source code, vhdl procedure, function signal generator.
dds
- 使用VHDL硬件描述语言实现了直接频率合成器的制作,并在Altera公司的CycloneII上得到实现,验证了代码的正确性。用户操作可以参照程序中的说明,请使用QuartusII6.0以上版本打开,低版本打开时会有错误提示-Using VHDL hardware descr iption language to achieve a direct frequency synthesizer production, and Altera s CycloneII be realized, to ver
PSK
- 关于PSK调制与解调的VHDL程序及仿真-PSK modulation and demodulation on the VHDL procedures and simulation
DDS
- 本代码可以用于产生正余弦信号波形,利用FPGA内部的ROM放置一个正余弦采样点的数据表格,通过循环取址的方法,实现波形连续输出。-This code can be used to generate positive cosine signal waveforms, using FPGA' s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of t
51-DDS
- 不仅包含FPGA源码还包含51单片机控制源码,已经实现DDS功能,绝对原创。-Includes not only the FPGA source code also includes a 51 SCM control source, has been achieved DDS functions, absolutely original.
DDS
- 这个一个基于FPGA的DDS原代码 可以生成正弦和余弦两种波形-This is a DDS code bepend on FPGA ,it can generate two waves.
8psk
- 利用DDS原理设计8psk的原代码,已通过调试-8psk principle design using DDS source code, which has passed the commissioning
DDS
- DDS数字频率合成的verilog代码,附有正余弦查找表等-DDS digital frequency synthesis verilog code, with a cosine look-up table, etc.
ddsfinal1
- verilog语言实现的dds代码,并行通信,生成四种波形,大赛编写的代码,modelsim仿真-verilog language dds code,modelsim debug
dds
- 用VHDL在quartarsII下编写的DDS程序代码-In quartarsII with VHDL code, prepared DDS
DDS
- 这个是在quartusii和matlab simulink下搭的dds的模型,已经经过仿真是可以的。并且已经转为vhdl代码。-This is quartusii and matlab simulink model to catch the dds, has been the simulation is possible. And has to vhdl code.
nco
- 数字接收机DDS中NCO设计,vhdl代码参考-NCO of DDS in a digital receiver design,vhdl code reference
vhdl-ad9910
- ad9910 DDS板 VHDL源代码,在Cyclone II FPGA上调试通过,主要文件说明: Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to s
dds
- VHDL的DDS代码,也就是直接数字式频率合成器设计-The DDS VHDL code, which is Direct Digital Frequency Synthesizer
dds
- 可以完成直接频率合成器功能的VHDL代码-VHDL code which can complete the function of Direct frequency synthesizer.