搜索资源列表
fifo_datapath
- verilog实现，串转并通过fifo再并转串，可以满足输入速率自由输出的一半时，输出仍可持续发送-verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
vga_pannel_design
- verilog代码写的控制vga显示的实例，利用状态机进行描述，很好的参考例子-verilog language write serial fifo instance, because the serial port speed is relatively slow, a lot of the interface will use fifo buffer
I2S
- 本代码提供一种音频I2S读取数据的verilog代码，并且向fifo写入-This code provides an I2S audio data is read verilog code, and write to the fifo
fifo2
- 异步fifo 先进先出 用于缓冲数据，用verilog HDL所写，在quartus II中测试通过，modelsim仿真-Asynchronous fifo FIFO for buffering data, using verilog HDL written in quartus II test through, modelsim simulation
asyn_fifo
- 本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by
FIFO64
- FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
fifo_datapath
- verilog实现，串转并通过fifo再并转串，可以满足输入速率自由输出的一半时，输出仍可持续发送-verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
SRAM_WR
- 本人自己经过实践检验的SRAM读写器，用Verilog编写的，可以作为FIFO使用。-I own proven SRAM reader, using Verilog prepared, can be used as a FIFO.
New_UART_verilog
- 这个是最新的UART的verilog代码，里边含有和UART相关的所有function,比如状态机，接收发送FIFO等相关代码。-New UART verilog sample code,Include FIFO code state mashine code ,recevier/trasmiter code
FT245BL_test
- (1)FT245BL芯片datasheet(2)test，USB 转FIFO 芯片测试的verilog程序-(1) FT245BL chip datasheet (2) test, USB transfer FIFO chip testing procedures verilog
syn_fifo_style_1
- verilog实现的，异步FIFO。所有代码在一个模块中。-verilog achieve, asynchronous FIFO. All code in a module.
fifo_verilog
- 16位FIFO的硬件电路，使用verilog实现。文件内含组合逻辑和寄存逻辑两种方法的实现，以及对应的testbench测试代码-16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code
asyn_fifo
- verilog asyn_fifo,内含详细说明,同步FIFO为TPRAM-asyn_fifo include detailed instruction，Synchronous FIFO for TPRAM
syn_fifo
- Verilog，syn_fifo ，内含详细说明，同步FIFO为TPRAM-Verilog, syn_fifo, containing detailed instructions for synchronous FIFO TPRAM
sync_fifo
- 同步fifo实现代码，包括的参数：数据宽度、fifo深度、地址宽度；状态信息包括：full, empty。-verilog RTL code which implement a synchronous FIFO function with data width, fifo depth, address pointer width parameterized.
axis_fifo
- VIVADO下使用verilog编码的axi fifo的简单使用，仿真通过，供初学者学习。-Use the following VIVADO verilog coding axi fifo simple to use, through simulation, for beginners to learn.
rx_tx_demo
- 用verilog实现的少量字符串的连续收发，添加了FIFO模块，稍微修改下就可以使用。-Receive a small amount of a continuous string of verilog implementation, added FIFO module, can be used under slightly modified.
fifo_pipeline_booth_multiplier
- fifo_pipeline_modified_booth_multiplier一个使用FIFO的Booth乘法器，并且使用了流水线描述方式，本程序给予verilog 语言-fifo_pipeline_modified_booth_multiplier, a booth multiplier using pipeline technology in verilog HDL language
uart_server
- 24路串口转1路串口服务程序, 包括FIFO模块，串口接收，发送模块，定时器模块，检测控制模块等。采用Verilog编写-24 way serial ports to 1 serial port, including FIFO module,RX module,TX module, timer module, detection and control module, etc.. Verilog preparation
SD_Card
- sdhc卡spi扇区读verilog例程。包含sdhc卡初始化模块及一个扇区读模块，扇区读完数据放在一个fifo中缓存，为之后的工作做准备，可以集成到自己的项目中。已经在闪迪8Gsdhc卡上亲测成功-sdhc card sector read spi verilog routine. Initialization module and a read module contains sdhc card sector, the sector read data in a cache fifo in