搜索资源列表
fir6dlms
- lms算法，自适应滤波器中使用fir滤波器对信号的码间干扰进行均衡-lms
fir
- vhdl code for fir filter
fir
- this file contain a descr iption in vhdl of a fir it contain three part well described to similate the behavior of the this type of filter
FIR_CODE
- 4-taps FIR VHDL code with testbench
VHDL_TipsTricks
- tips to design fir filter step by step
34105908-Multipliers-Using-Vhdl
- ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and
FIR_IP_lowpass
- 8阶FIR_IP的VHDL代码以及QuartusII的顶层文件-FIR_IP the VHDL code of order 8 and the top-level file QuartusII
fir(1)
- 基于fpga的fir数字滤波器的设计的用QUARTUS II 做的VHDL语言的源代码-The fir fpga based design of digital filters QUARTUS II to do with the source code for VHDL,
FIR
- 采用vhdl语言 设计FIR滤波器，经调试好使，献给广大硬件开发的朋友参考学习-FIR filter design using vhdl language, so that upon commissioning, the development of friends dedicated to the general hardware reference learning
Digital-Signal-Processing-with-FPGA
- FPGA结合DSP设计，如FIR、IIR滤波器，CORDIC算法,多重采样率信号处理，FFT,有对应的VHDL/Verilog 代码code-FPGA Combines with DSP, FIR 、IIR Digital Filters,CORDIC,FFT,Adaptive Filters，VHDL/Verilog code
FIR-LOOP-
- 数字接收机中的FIR滤波器，环形滤波器设计参考,VHDL代码-the FIR filter， loop filter design in a digital receiver,vhdl code
fir-filter
- fft的vhdl实现源代码，具体的有心情有兴趣的可以自己下载下来看下，因为我也是在入门中不懂。-fft verilog HDL
FIR
- This FIR code wriiten in VHDL. This is 16 bit FIR tested on Spartan 3E kit-This is FIR code wriiten in VHDL. This is 16 bit FIR tested on Spartan 3E kit
VHDL
- 基于FPGA的IIR滤波器的各模块VHDL程序- such as in science and project technique. Compared with FIR digital filter, IIR digital filter can get high selectivity with low factorial.
26352153-VHDL-Coding-for-FIR-Filter
- VHDL filter design powerpoint
FIR---ALEX
- Filter c language, better validation, able to run the filter C language-FIR filter VHDL, you can use, though a bit......
VHDL
- 这个是基于一下的要求设计的：1、输入输出数据宽度为12位， 2、阶数为4阶段线性相位FIR滤波器， 3、类型为：低通。-This is based on what the requirements of the design: an input and output data width is 12, 2, the order of the four stages of linear phase FIR filters, 3, type: low pass
designing-of-FIR-filer-based-on-FPGA
- 该文件是基于FPGA设计FIR滤波器设计的VHDL语言代码。-designing of FIR filer based on FPGA
FIR
- an FIR code which is writen in vhdl. this entity has clk and reseet inputs, and the filter output is provided as well. the coefficients of the filter are passed using a set of constants.
FIR
- fir数字滤波器，VHDL语言编程，先通过MATLAB计算得到参数。-fir digital filter VHDL language programming, first obtained by MATLAB calculated parameters.