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UCLINUXS3C44B0移植
- 51 ip 核 vhdl 原代码 s3c44b0x 移植代码 -51 ip nuclear VHDL source code s3c44b0x transplant
Altera-SDRAM_controller-IP-CORE
- Altera的SDRAM IP核代码，支持源码创作-Altera s SDRAM IP core code to support the creation of source
Creating-Project-and-IP-Core-in-ISE
- 本文介绍了在ISE环境中如何新建工程，并且定义设置IP核进行开发-This article describes how new construction ISE environment, and define the settings IP core development
fir-ip-vhdl
- altera quartus fir ip核 vhdl程序 含测试文件-altera quartus fir ip nuclear vhdl program including test files
grey-code--FIFO-IP-core
- 基于格雷码的FIFO的IP核，调试可用于通信接口的队列传输。-Gray code based on FIFO IP core, debugging can be used for communication queue transmission interface.
UART-IP-based-on-queue
- 基于队列传输的UART的IP核程序，已调试可直接使用。-Queue-based transmission of UART IP core procedures have been debugging can be used directly.
SPDIF-interface-IP-core
- SPDIF数字音频接口的的程序，已写成通用IP核形式。-The program SPDIF digital audio interface has been written in the form of common IP core.
FPGA-IP-core
- FPGA中IP核的调用 适用于初学者,里面是两个PPT 其中一个主要讲RAM&ROM IP CORE的调用-usage of FPGA IP core ,Suitable for beginners
CAN-IP-Core
- CAN IP Core can硬件的IP核，用于cpld和fpga编程can接口-CAN IP Core
CAN-IP
- CAN控制器IP核(可直接在Nios II中使用)-CAN controller IP core (Nios II can be used directly in the middle)
IP
- USB+UART+I2C+VGA+ARM7+MC8051 altera IP核-USB+UART+I2C+VGA+ARM7+MC8051 Verrlog VHDL
GTP-ip核使用
- 主要对GTP模块进行划分，主要对功能模块在中文描述(GTP module is mainly divided into the main function module described in Chinese)
SPWM信号产生系统IP软核设计及验证
- 针对电力电子领域的需求，采用自然采样法设计了一个全数字三相SPWM信号产生系统IP软核．通过数字频率合成技术实现了对电源频率的辅确控制．使电源频率精度达到16位．其中。通过调节控制参数．分别实现了电源频率与载波频率的7级、8级控制．最后。搭建了基于FPGA的测试系统．验证了系统功能的正确性．(According to the requirement of power electronics, the natural sampling method for the design of a full
XilinxFree.lic
- 这是许可在Xilinx Vivado 2015利用免费的IP核生成(This is the license to utilize free IP core generation in Xilinx Vivado 2015)
RX_IP_Source
- 串口接收ip核，配合 nios 使用，减少cpu资源开支。(uart receive TX_IP_Source)
TX_IP_Source
- 串口发送ip核，配合 nios 使用，减少资源开支。(uart transmit TX_IP_Source)
PG007_Xilinx RapidIO IP阅读笔记
- srio pg007 中文，iP核介绍和仿真步骤(The iP core is introduced and simulation steps)
AMBA_VIP
- AMBA 总线IP 核Verilog代码(AMBA bus IP Verilog code)
LaSaNewNB_M88E1111_TCP1000mhz
- 用FPGA，基于M88E1111芯片实现的TCP/IP协议的千兆网，将协议封装成IP核(With the FPGA, the TCP/IP protocol based on the M88E1111 chip is used to encapsulate the protocol into IP core)
can_v3_2
- XILINX 的IP核CAN V3.2的VHDL程序(XILINX's IP core: CAN_V3.2-VHDL)