搜索资源列表
lms
- 文件中为lms算法的ise工程,其中包含了lms算法的fpga实现的verilog程序以及testbench,很好的在FPGA上实现了lms算法,还有一些调试程序的总结-Ise project file for lms algorithm, which contains the lms algorithm fpga verilog program to achieve and testbench good lms algorithm implemented on FPGA debugger su
verilog_UART_100MHZ
- 自己写的verilog UART程序,前仿真后仿真,下到板子里都对,ISE的-Verilog UART write your own program, before simulation after simulation, are right next to the plate yard, ISE' s
Mstateei
- 米勒解码器的状态转换模块。用verilog语言编写写,ISE为开发环境 ,经测试可直接使用。 -Miller decoder state transition module. Verilog language writing, ISE development environment has been tested and can be used directly.
calculator
- 基于赛灵思的spartan-3e开发板的语音智能计算器的设计,开发语言verilog,开发软件ISE,可以根据ucf文件理清引脚关系。应用者需要对开发板和fpga设计有一定的了解!-Development board based on Xilinx spartan-3e voice smart calculator design, development languages Verilog, developing software ISE, according to
frequency
- 能够检测方波正弦波以及锯齿波的频率,并且以及试过可以运行,采用的开发环境是ISE,编程语言是Verilog-Able to detect a square wave frequency of the sine wave and sawtooth wave, and as well tried can run the development environment is the ISE, the programming language is Verilog
RS232
- RS232与电脑串口的通信控制代码,verilog hdl代码,里面包括完整的ISE工程-RS232 and computer serial communication control code, verilog hdl code, which includes a complete ISE works
hdb3
- 该代码使用Verilog HDL语言编写的,能够对HDB3码进行编译,该文件是完整的,可以直接在ISE软件上运行-Compile the code using Verilog HDL language, HDB3 code, the file is complete, you can run directly in the ISE software
a1
- 1 bit MUX 用ISE写的1bit MUX的verilog code 可以在ISE上模拟1bit MUX的运作-1 bit MUX It is a file of verilog code to design a 1 bit MUX. It is design by ISEbit
Useful_data
- Full flow descr iption of the flow of developing the verilog code in ISE and steps in implementing and executing in fpga
ImageRotate
- 利用verilog实现图像旋转。本程序是基于XILINX公司的ISE实现的。-Verilog image rotation. This procedure is based on XILINX' s ISE.
carry_select
- 上传的代码是基于Xilinx下的ISE开发平台,用Verilog语言编写的carry_select加法器。-Upload the code is based on the Xilinx ISE development platform, the the Verilog language of carry_select adder.
6678_pci_duplex
- PCI9656 的控制,ISE 12.2,verilog编写,slave模式-PCI9656,verilog,ISE 12.2,using verilog,SLAVE mode
music
- 利用FPGA模拟弹钢琴的Verilog代码。在Xilinx ISE 14.3 编译通过-Using FPGA Verilog code simulation play the piano. Compiled by Xilinx ISE 14.3
EMAC6
- verilog实现的FPGA三态以太网链路层通信代码,里面有状态机,并按各个模块的功能分了文件夹,还有说明文档,自定义帧的产生和接收,开发环境为Xilinx ISE,测试无误。-verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well a
DigitalWatch
- 用verilog数字钟,并且在ise上验证,可以显示分秒,并且可以对分和秒进行调整-Verilog digital clock, and verified in ise, can display every minute, and you can adjust the minutes and seconds
zhongzhilvbo
- xilinx ise 与modesim联合验证中值滤波 含verilog源程序和整个工程文件-the xilinx ise modesim median filter containing joint verification verilog source, and the entire project file
fpga-fir
- xlinx fpga 利用verilog语言实现fir滤波器功能,完整ise工程文件直接可以使用-xlinx fpga verilog language the fir filter function, complete ise project file can be used directly
CooperativeCommunication
- 1. 研究空时分组码的编译码原理及算法; 2. 研究了几种不同的协作分集系统模型和协作分集协议; 3. 将空时分组码编译码器与协同通信用硬件描述语言Verilog实现,并在ISE集成环境中综合仿真,结果正确后下载到FPGA电路板上; 4. 用示波器观察输出数据是否正确,验证空时分组码协同通信的性能。 -1. Decoding Principles of space-time block codes and algorithms 2. Study several differen
AXI_MIG
- ISE生成的AXI接口的MIG,内存控制器,语言:verilog-ISE generated the AXI interface MIG, memory controller, language: verilog
I2C-bus-based-on-FPGA
- 基于FPGA设计I2C总线,使用Verilog语言,ISE环境,含有仿真结果-I2C bus based on FPGA design using Verilog language, ISE environment containing simulation results