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i2c
- verilog语言实现i2c,在ise中调试仿真-verilog language i2c, debugging simulation in ise
counter
- 本文介绍了基于FPGA的数字频率计的设计方法,设计采用硬件描述语言Verilog ,在软件开发平台ISE上完成,可以在较高速时钟频率(48MHz)下正常工作。该数字频率计采用测频的方法,能准确的测量频率在10Hz到100MHz之间的信号。-This article describes the FPGA-based digital frequency meter design method using hardware descr iption language Verilog, ISE on t
top
- 在ISE环境里,用verilog语言编写得数码管显示程序,能动态计数-In the ISE environment, use the verilog language digital display program was able to dynamically count
AMI
- 在ISE软件环境下,用Verilog HDL语言实现通信中的AMI码的编码和译码,并有仿真波形。-In the ISE software environment, using Verilog HDL language for communication in the AMI code encoding and decoding, and a simulation waveform.
shuzipaobiao
- 在ISE环境下用Verilog HDL写的一个简易的数字跑表,最大量程为60分钟,精确到毫秒级,有复位键和暂停键。-In the ISE environment, using Verilog HDL to write a simple digital stopwatch, the maximum range is 60 minutes, accurate to the millisecond, the reset button and pause button.
traffic-light-FSM
- 在ISE环境下用Verilog代码分别用一段式和三段式来实现交通灯,并产生仿真波形。-In the ISE environment, were used in Verilog code to implement a three-stage type and traffic lights, and generate the simulation waveforms.
can-bus
- CAN总线控制器的VERILOG工程文件,很实用,工程是ISE可以打开,也可以只使用工程里面的代码-can bus project with VERILOG
DDS
- 在ISE环境中,运用verilog语言实现DDS(直接数字式频率合成器(Direct Digital Synthesizer)的英文缩写)的功能-In the ISE environment, use verilog language DDS (direct digital frequency synthesizer (Direct Digital Synthesizer) in abbreviation) of the function
verilog_lab_solution
- Verilog 实验代码。。。经典的,里面都是完整的项目文件。 ISE环境。-Verilog test code. . . Classic, which is a complete project file. ISE environment.
usb_latest.tar
- USB 源码。Verilog实现的USB程序,用ISE打开工程文件即可-USB verilog code。-Verilog implementation USB program, open the project file with the ISE can be
filer_pipeline
- 基于流水线的滤波器的设计与实现,verilog代码,xilinx,ISE,-Based on the assembly line of the design and realization of the filter, verilog code, xilinx, ISE,
sincount
- 用verilog语言开发的,ise产生正弦波的工程文件-Ise generate the triangular wave file
sdram
- 在ISE环境中,利用verilog语言编写的SDRAM的控制,已经通过功能仿真,其中PLL部分并没有加入,使用时可以自行加入PLL模块。-Verilog language in the ISE environment, the use of SDRAM control, through functional simulation, which the PLL part and did not join, can join the PLL blocks.
VCO
- 压控振荡器的FPGA实现,Verilog语言完成。编译环境 ISE 13.2-The vco FPGA realizing, Verilog language completed. Compile environment ISE 13.2
comparator
- 使用verilog语言,在FPGA开发工具ISE上实现比较器功能。-The use of Verilog language, in FPGA ISE development tools to achieve the comparator function.
flip_flop
- 使用verilog语言,在FPGA开发工具ISE上实现触发器功能。-The use of Verilog language, in FPGA ISE development tools to achieve the flip-flop function.
lcd
- lcd 1602 verilog ise xilinx-the lcd 1602 Verilog ise xilinx
mux16
- mux 乘法器 verilog ise xilinx-the mux multiplier Verilog ise xilinx
Viterbi11111
- 使用Verilog编写的vertbi译码模块,ISE12.2下编译通过,主用是调用ISE下的Vertibi核设计实现的。-Written using Verilog vertbi decoding module, ISE12.2 compiled by the main use is to call ISE the nuclear Vertibi designed to achieve.
ttraafficLighr
- <p>交通灯状态机的实现,用verilog HDL编程与开发,Xillinx ISE 6仿真,在实际电路中的到验证. 已通过测试。</p> -<p> The implementation of the traffic light state machine, using verilog HDL programming and development, Xillinx ISE 6 simulation, to verify the actual circui