搜索资源列表
USB IPcore（带说明）
- USB IPcoreIP核，包含文档（带说明）-USB IPcoreIP nuclear contains documents (with the note)
usb_funct
- usb1.0的核，有详细的usb核的设计源码，用verilog语言编写，同时附有相关的设计文档，质量不错-usb1.0 nuclear, nuclear usb detailed design source, using Verilog language, along with documents related to the design, quality good
PowerSwitch.2005-02-20
- 软USB核的电力开关PowerSwitch-soft USB nuclear power switching PowerSwitch
USB_1.1IP核
- 这是USB的一个机遇FPGA的IP核设计。欢迎大家使用
USB.rar
- 用VHDL实现的USB IP核，大家可以参考下,Use VHDL to achieve USB IP core, we can refer to the following
usb11.rar
- 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。,Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
usb_funct[1].tar
- usb2.0的IP核，可在QuartusII或MaxPlusII环境下实现编译和生成ip核-usb2.0 IP nuclear, QuartusII or the environment under MaxPlusII compile and generate nuclear ip
USBipcore
- usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
can
- 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
slaveController
- 对USB的从机设备的IP核进行了重新设计并在一定程度上进行了优化-On the USB device from the IP core has been redesigned to some extent, is optimized
RTL
- 对usb设备控制的ip核进行了重新设计并进一步优化-Usb device on the control of nuclear ip has been redesigned and further optimize
USBreader
- USB文本阅读器，主要涉及SOPC技术，NIOS软核编程，供学习参考用-USB text reader, mainly related to SOPC technology, NIOS soft-core programming for the study and reference
1
- 15个免费的IP核 usb11,i2c,pci_core,video_compression_systems等等.-15 free IP core usb11, i2c, pci_core, video_compression_systems and so on.
USB_xilinx
- USB应用的IP核心，需要深入了解 核心的行为。建立本 诀窍是大大简化了全面 参考应用。-Application of IP-Cores requires in-depth knowledge of the core’s behavior. Building up this know-how is greatly simplified by comprehensive reference applications.
UART_Xilinx_vhd
- USB IPcoreIP核 包含文档(带说明)-USB IPcoreIP core includes a document (with instructions)
usb_latest.tar
- 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s，需要再外扩一个PHY。-This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
Usb_ISP1362
- 飞利浦公司Usb芯片ISP1362在nios中的IP核，可以用-Philips Usb-chip ISP1362 in nios in the IP core, you can use
USB
- Workbench 5.30评估版软件 利用上述开发软件，核心处理器采用基于Cortex-M3核的LPC1700芯片外围USB调试程序。直接打开工程文件就可轻松实现调试-Workbench 5.30 evaluation version of the software development using the above software, the core Cortex-M3 processor core based on the LPC1700 chip external USB de
verilog-usb--protel-design
- 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
USB-1.1-IP-CORE-VHDL
- USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code