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dds正弦发生器代码
- 讲述了dds直接数字频率合成的基本原理,同时用VHDL语言编写dds原代码用于生成正弦波,并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for sim
DDS_信号源
- dds 精确步进100HZ.拨码开关选择FSK,FM等功能.最高频率25M,DA芯片9760.VHDL编写
生成4种方式的DDS输出的读表程序的VHDL源代码程序
- 生成4种方式的DDS输出的读表程序的VHDL源代码程序.rar
DDS.rar
- FPGA控制AD9854的源文件,verilog,附有简单文档。,FPGA to control the AD9854 source file, verilog, with a simple document.
ddfs.rar
- 基本FPGA的DDS信号发生器,可产生1-1MHZ任意频率的三角波,方波,锯齿波,正弦波,Basic FPGA-DDS signal generator, can produce 1-1MHZ arbitrary frequency triangle wave, square wave, sawtooth, sine wave
cordicDDS
- Cordic算法实现DDS的Verilog 源码,14位精度,非常实用的。-DDS algorithm Cordic the Verilog source code, 14-bit accuracy, very practical.
costas的verilog程序
- costas的verilog程序,包含乘法器,DDS,鉴相器,环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
test_ad9852
- 使用FPGA来控制DDS信号的产生,从而达到高频信号产生的目的。使用的DDS芯片为AD9852,在QuartusII下编写。-Using the FPGA to control the DDS signal generation, so as to achieve high-frequency signal generation purposes. Use of DDS chip AD9852, in the QuartusII prepared.
AD9954_test
- AD公司DDS芯片AD9954的Verilog测试程序-VerilogHDL test program of DDS chip--AD9954 ,producted by AD company
singnal
- VHDL实现通用通信信号源,包括sin,cos,方波,三角波,BPSK,GMSK,ASK,16QAM等信号的产生以及DDS,PLL的VHDL系统代码-VHDL implementation of universal communication sources, including sin, cos, square, triangle, BPSK, GMSK, ASK, 16QAM and other signal generation and DDS, PLL system, the VHDL
24_bit_register
- 自己使用VHDL语言编写的24位寄存器.主要用于DDS中-24bit_register
AM
- FPGA内AM调制工程。内带调制波、载波生成。关键词:FPGA verilog AM DDS-AM modulation works within the FPGA. Within the band modulation wave generated carrier. Key words: FPGA verilog AM DDS
clk
- 现代电子系统课程设计 基于DDS技术利用VHDL设计并制作一个数字式移相信号发生器。 (1)基本要求: a.频率范围:1Hz~4kHz,频率步进为1Hz,输出频率可预置。 b.A、B两路正弦信号输出,10位输出数据宽度 c.相位差范围为0~359°,步进为1.4°,相位差值可预置。 d.数字显示预置的频率(10进制)、相位差值。 (2)发挥部分 a.修改设计,增加幅度控制电路(如可以用一乘法器控制输出幅度)。 b.输出幅度峰峰值0.1~3.0V,步距0
sin125
- 用FPGA实现DDS的信号发生器(正弦波125kHz)-Using FPGA to achieve DDS signal generator (sine wave 125kHz)
high_speed_tap8_DDS
- 用verilog编写的高速8路并行dds模块,用于与高速da(1ghz或以上)接口产生任意频率正弦波,模块已经经过工程验证,用于产品中。-Verilog prepared with high-speed 8-way parallel dds modules for use with high-speed da (1ghz or above) interface have any frequency sine wave, the module has been proof for the prod
dp_test
- 本程序是用VHDL语言编写的,其中包括并口通讯,DDS电机调速,编码器信号处理等,对研究这方面的工程人员有一定参考作用-This procedure is used VHDL language, including the parallel port communication, DDS motor, encoder signal processing and so on, to look at this area of engineering staff have a certain refe
example10
- :正弦波发生器例程,包括了直接数字频率合成(DDS)的原理以及如何应用CPLD产生频率可控频率的正弦信号。-: Sine wave generator routine, including a direct digital synthesizer (DDS), as well as the application of the principle of frequency control CPLD generated sinusoidal signal frequency.
FPGA_Examples
- 《FPGA嵌入式应用系统开发典型实例》-书的光盘资料,该资料是用VHDL语言编写,作者:叶淦华-" FPGA embedded applications typical example of system development" - the book' s CD-ROM, the information is written in VHDL, the author:叶淦China
PSK
- 关于PSK调制与解调的VHDL程序及仿真-PSK modulation and demodulation on the VHDL procedures and simulation
leijiaqi
- 累加器,一个加法器和一个寄存器构成的累加器,其用途是用于DDS技术的相位累加器 -ACC