搜索资源列表
16×4bitFIFO
- 16×4bit的FIFO设计,VHDL语言编的的,能在ISE上仿真出来结果。
sram
- FPGA向SRAM中写入数据(VHDL编程),包含通用fifo,sram等
fifo8x9
- 8位深,9位宽FIFO VHDL源码设计,如需改进可在此基础上扩展
asyn_FIFOrealizedbyVHDL
- 一个比较经典的用VHDL实现的FIFO论文
uart_regs
- 可以直接下载到芯片用的带有FIFO的完全UART程序,vhdl语言编写。
usb
- 使用68013的测试程序,包含68013固件程序(采用slave FIFO bulk同步读写,EP2 OUT,EP6 IN),驱动,PC端测试用程序。CPLD的VHDL代码
fifo_vhdl
- 基于vhdl语言实现的fifo控制器。经过仿真及实际测试-failed to translate
lcd-code
- 比较完整的LCD接口代码,verilog编写,分为6800和8080两种CPU接口,且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
ref-sdr-sdram-verilog
- SDRAM的vegilog代码,做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
VGA-VerilogHDL
- 用Verilog HDL编写的VGA显示驱动程序-Verilog HDL prepared with VGA display driver
mini_fifo
- 另外一个用VHDL源码编写的FIFO模块程序,可以比较一下和FIFO有什么区别.-Another, prepared by using VHDL source FIFO module procedures, you can compare and What is the difference between FIFO.
SYNC_FIFO
- its simple fifo.which is used to first in first out for vhdl source code
fifo_memory
- 用vhdl设计的一个FIFO存储器-Vhdl design with a FIFO memory
fifo1
- 用VHDl写的FIFO 如果刚学VHDL 看看此程序很有用的-By the FIFO write VHDl learn if VHDL just take a look at this program very useful
de2_lcm_ccd_sram
- 这是altera公司DE2的lcm-ccd-sram的代码,希望对大家编写有用-this code based on the altera DE2 board
char_fifo
- character FIFO in VHDL very speed
simpleFIFO
- FIFO的VHDL程序,硬件描述语言源码-FIFO process of VHDL hardware descr iption language source code
DEMO_46_FIFO
- 这是用vhdl语言详细描述一个fifo的全过程,请大家下载-This is the vhdl language with a detailed descr iption of the whole process of fifo, please download
fifo2
- FPGA的异步先入先出程序,VHDL的fifo-VHDL and fifo