搜索资源列表
hdlc
- HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
FIFO_Design
- 一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation
FPGA_FIFO
- 使用Verilog编写的同步FIFO，可通过设置程序中的DEPTH设置FIFO的深度，FIFO_WRITE_CLOCK上升沿向FIFO中写入数据， FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising
CuFIFO
- fifo的vhdl代码,比较简单，适合初学。-fifo the VHDL code, is relatively simple, suitable for beginners.
TS_sychrous_check
- 该模块主要用于MEPGII TS流同步检测。当连续检测到3个TS包同步时，输出一个同步有效信号，在该同步信号的驱动下，TS包写入FIFO中。该模块对检测TS包的有无及是否同步特别有效，希望对做数字电视的朋友有所帮助。-The module is mainly used for synchronous detection MEPGII TS stream. When detected in three consecutive TS packets simultaneously, the outpu
asyn_fifo
- verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
usbin_v1.7
- 用于cy7c68013与fpga的从FIFO通讯.版本1.7-For the CY7C68013 and FPGA communications from the FIFO. Version 1.7
fifoi
- 基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控-Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable
ps
- RS(204,188)译码器的设计 异步FIFO设计 伪随即序列应用设计 CORDIC数字计算机的设计 CIC的设计 除法器的设计 加罗华域的乘法器设计-RS (204188) decoder design of asynchronous FIFO design application design sequence was pseudo-CORDIC design of digital computer design CIC divider design Le Hua
video_process_base_on_DSPandFPGA
- 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型 化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管
75448172geleicounter
- 这是异步fifo的vhdl实现代码，已经在FPGA上通过实践证明，运行状态良好-This is the asynchronous fifo realize the VHDL code has been adopted in the FPGA Practice has proved that running in good condition
clk
- 通过一个主时钟信号完成异步FIFO读写时钟信号的产生。编译通过实现功能。-Through a master clock signal the completion of asynchronous FIFO read and write clock signal generation. Compiler through the implementation function.
ram
- a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc
rtl
- 液晶model 设计LCD 并口模式下的仿真model-LCD FIFO model
fifo_core
- 经典的FIFO实现源码，里面有三种类型，是xilinx工程师写的，经典-Classic source FIFO implementation, there are three types, are written by xilinx Engineer, classical
asynFifo
- 异步fifo在IC设计中，非常重要；是异步时钟域同步方法-Asynchronous fifo in IC design, is very important are asynchronous clock domain synchronization
Flash_ROM_lab
- 用SmartGen生成一个256*8的大小同步FIFO，并通过串口发送数据初始化FIFO。然后，再通过串口返回到上位机的串口调试程序显示，确认数据是否正确。-SmartGen generated with a size of 256* 8 Synchronous FIFO, and sending data through the serial port to initialize FIFO. And then back through the serial port to the PC ser
usb
- USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control,
fifo1
- 异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been
FIFO
- FIFO，vhdl实现，希望可以有帮助,大家加油-FIFO VHDL