搜索资源列表
embedded_risc
- 一个嵌入式RISC CPU 的Verilog 设计源码,可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
filter 代码
- 用verilog实现滤波器的功能,通过软件综合仿真,在利用FPGA实现-using Verilog filter function to achieve through integrated simulation software, the use of FPGA
5-3-10_ModelSim
- 综合仿真程序,含全加,解码,滤波等多种功能 Verilog语言-integrated simulation programs, including the All-Canadian, decoding, filtering and other functions Verilog language
u-uart
- 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
div5
- 简单的VERILOG五分频电路描述,可综合。已经过检验-simple verilog 0.2-frequency circuit descr iption can be integrated. Have been tested
simple_fifo
- verilog HDL原码 一种简单的同步FIFO原码,可以被综合-verilog HDL original code a simple synchronous FIFO original code, which can be integrated
djpeg_vlsi
- jpeg解码电路,是verilog编写的,可以综合,很有实用价值。-jpeg decoder circuit, is prepared verilog, synthesis, very practical value.
sarm9beta
- arm9 架构简单core实现,可以综合,有实现步骤和说明,verilog代码编写。-arm9 core framework to achieve a simple, comprehensive, implementation steps and notes verilog code prepared.
8088verilog
- intel 8088 架构的verilog代码,可以综合下载,在fpga上实现8088调试。-intel 8088 verilog structure of the code can be integrated download, fpga achieved in 8088 debugging.
Synthesisofverilog
- 一篇有用的Verilog语言综合问题研究-a useful comprehensive Verilog language study
ADC_16bit
- 用verilog硬件描述语言编写的16位数模转换器的源代码,可以综合-with verilog hardware descr iption language of 16 Digital to Analog source code can be integrated
CommandResponse
- verilog语言写的sdram控制器—命令响应模块代码,经过测试,逻辑正确,可编译,可综合-verilog language written sdram controller-order response to the code, tested, logically correct, compiler, integrated
8251_8055_verilog
- 8251和8055的verilog源码,可进行综合和仿真,是学习SOC的好资料!-8251 and 8055 verilog the source, and integrated simulation, SOC is a good learning information!
FIFO
- 一个可以综合的Verilog 写的FIFO存储器 内附文档说明-a comprehensive Verilog can write FIFO memory attached document shows
FIFO_Syn
- 同步FIFO功能,verilog语言描述,通过了modelsim 6.0 仿真,Quartue综合
4VerilogFIFO
- 一种新的FIFO实现方法,verilog描述,通过modelsim 6.0 仿真,Quartue综合
circularbuffer
- Circular_Buffer,流水线型多位缓存器,verilog语言描述。通过modelsim 6。0仿真,quartus 综合通过。
89_full_adder
- full adder设计代码,verilog 语言描述,通过modelsim 仿真,quartus综合
FIFO-DC
- FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进行综合
bbb
- AVS运动补偿电路的VLSI设计与实现 提出了一种基于AVS标准的高效的运动补偿电路硬件结构,该设计采用了8 X 8块级流 水线操作,运动矢量归一化处理和插值滤波器组保证了流水线的高效运行以及硬件资源的最优 利用。采用Verilog语言完成了VLSI设计,并通过EDA软件给出仿真和综合结果。