搜索资源列表
keeloq encoder
- this code is a keeloq encryption verilog code-keeloq encryption verilog code
CTC_Encoder
- duo-binary turbo encoder for wimax 802.16e
LIB5002_CW_8b10b_enc
- Verilog 8b10b encoder source code
rs_encoder
- reed solomon encoder used in DVB verilog code.
decoder-and-encoder
- codes for different modules in verilog
8-3-priority-encoder
- 用verilog硬件描述语言实现的8-3优先编码器-8-3 priority encoder
encoder-8b10b
- 可以实现8b10b编码，verilog源程序，经过测试-8b10b Encoder
JPEG-Encoder
- JPEG 编码器的verilog实现，已经在XILINX SPARTAN6上实现并验证。-The JPEG encoder verilog implementation has been implemented in a Xilinx SPARTAN6 and verify.
encoder
- 8线-3线编码器，用verilog语言实现的-8 lines-3 line encoder, using verilog language
dvi-code-verilog
- dvi encoder and decoder for fpga
Huffman-Encoder
- 本压缩包，包换一个用verilog语言实现的huffman编码源程序，同时给出了众多论文和基础知识的文档资料，一应俱全。-The compression package, shifting one using huffman coding verilog language source code, and gives basic knowledge of many papers and documentation, everything.
verilog-source-codes
- the attached programs are source codes of 4-bit ring counter, 16x1 mux, 8x3 priority encoder, 4x16 decoder, full subtractor using two half subtractors
MATLAB-and-Verilog-codes
- there are 5 files. the first two codes are written in Matlab as m-files in control system design to show step responses. in contrast, the final three codes are written in verilog ( Quartus II) used in Altera one of them for BCD adder and the other fo
Encoder
- The program using verilog language to decribe encoder x1 x2 and x4
PCD encoder
- ISO14443 A PCD encoder for RFID chip design verification. Verilog code
verilog-juanjima
- 卷积码是一种重要的前向纠错信道编码方式，其纠错性能常常优于分组码，且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块，译码器采用全并行结构，译码速度快-Convolutional code is an important forward error correction channel coding method, and
CCIR656-encoder
- a source code of CCIR656 encoder in verilog HDL with corresponding testbench and a snapchat of the resulting waveform-a source code of CCIR656 encoder in verilog HDL with corresponding testbench and a snapchat of the resulting waveform
encoder
- The code for 8 to 3 encoder is written in Verilog language.
FPGA-H265-Encoder
- H.265的FPGA实现！！使用Verilog语言开发。-H.265 FPGA implementation! Developed using Verilog language.
BCH_VLSI
- 使用HLS完成BCH编码的运算通路的设计，纯组合逻辑，对于65nm工艺可跑上1GHz。已经组合逻辑分为了多个部分，可在每一个部分之间插流水线。 附上可综合的纯RTL Code以及C++代码，以及Modelsim仿真。 可通过我的优化选项来学习如何优化HLS工具生产的代码。(BCH Encoder realized using HLS tool. Combinational logic.)