Lempel–Ziv–Storer–Szymanski compression encoder verilog code

针对数字基带传输系统中HDB3信号的特点，采用基于FPGA的Verilog HDL语言，实现HDB3数字基带信号的编码器设计,共有插V、插B、单双极性变换模块，最终能在FPGA实现。-For digital baseband transmission system HDB3 signal characteristics, based on FPGA Verilog HDL language, designed to achieve HDB3 encoder digital baseband si

关于BCH的编码器和译码器，可实现16位，32位，64位，128位的编码和译码纠错，2位纠错，Verilog实现-On the BCH encoder and decoder, can achieve 16-bit, 32-bit, 64-bit, 128-bit encoding and decoding error correction, 2-bit error correction, Verilog implementation

8-3优先编码， 1、学会用Verilog语言的描述方式来设计电路； 2、熟悉8—3优先编码器，并用Verilog语言实现其功能； 3、掌握Cyclone系列FPGA的程序加载，熟练掌握将.sof文件加载到实验箱中，实现8—3优先编码器的效果。(8-3 priority coding, 1. Learn to design the circuit with Verilog descr iption; 2. Familiar with 8-3 priority encoder and i