搜索资源列表
Codes-and-Reports
- Verilog Source code for arbitrary waveform generator- simple DDS algorithm codes run on Xilinx Spartan-3E fpga to show output on dac pin. Please see the included report. its really simple to implement. all source code is given.
CODE_GEN
- 北斗、GPSC/A码生成器的verilog ，输出速率可调，使用verilog编写- FPGA-based GPS receiver complete code of the spreading code generator design using verilog language
BCH_EN
- 基于FPGA的GPS/BD信号发生器中BCH编码发生器模块，使用verilog编写- FPGA-based GPS/BD signal generator BCH code generator module, using verilog write
NAVI
- 基于fpga的GPS导航数据发生器，使用verilog编写- Fpga-based GPS navigation data generator, using verilog write
spi
- 基于system generator的SPI协议的设计，能自动转换成verilog或VHDL语言-Based on the system of the generator SPI protocol design
CLOCK_GENERATOR
- 一个verilog时钟发生器源代码，能够满足最小时间间隔0.1ns的时钟计时要求。-A clock generator verilog source code, to meet the minimum time interval of 0.1ns clock timing requirements.
SIN_GNT
- LPM_ROM定制。简单的正弦波发生器。 Verilog HDL语言设计。 EP4CE15F17C18N实测可用。-LPM_ROM customization. Simple sine wave generator. Verilog HDL designs. EP4CE15F17C18N measurement available.
DDS
- 基于fpga的正余弦波形发生器，Verilog代码，测试通过。-Cosine waveform generator fpga based, Verilog code, the test passes.
edasingene
- 基于FPGA的正弦信号发生器的设计，用verilog语言实现，可调整频率和周期。-FPGA design based on sinusoidal signal generator with verilog language, adjust the frequency and period.
Local_barker
- 巴克码发生器Verilog程序，用于数据传输的帧同步-Verilog program Barker code generator, a frame synchronization for data transmission
clk_gen
- this is a clock generator program by using concurrent language verilog hdl with xilinx ise.
sinwave-genertor
- sinwavw generator code in verilog this will helpful for generating a sinave without using a cordic
DDS-MY-WORK-1
- FPGA模拟数字信号发生器DDS verilog-FPGA analog and digital signal generator DDS verilog
I2C_Single_Master
- I2C Single master written in Verilog Libero Designer core generator.-I2C Single master written in Verilog Libero Designer core generator.
reed_solomon_decoder
- Reed Solomon Decoder written in Verilog Libero core generator.-Reed Solomon Decoder written in Verilog Libero core generator.
UART
- General purpose UART written in Verilog Libero core generator.-General purpose UART written in Verilog Libero core generator.
RX_ASYNC_for_module_UART
- Rx Async for module UART written in Verilog Libero Designer core generator.-Rx Async for module UART written in Verilog Libero Designer core generator.
TX_ASYNC_for_module_UART
- Tx Async fpr module UART written in Verilog Libero core generator.-Tx Async fpr module UART written in Verilog Libero core generator.
buzzer
- 基于EP2Q208C8,用Verilog编写的蜂鸣器音乐发生器，蜂鸣器能够根据开关的选择对应地弹奏曲子-Based EP2Q208C8, written using Verilog buzzer music generator, buzzer able to play the song based on the corresponding selection switch
ahb_master
- AHB master system generator in verilog