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modulo-2^n-2^k-1-adder
- 用Verilong语言编写的模2^n-2^k-1加法器，该加法器多用于基于余数系统的蒙哥马利模乘运算。 -Implementation of modulo 2^n-2^k-1 adder Using Verilog.This adder can be use for RNS Montgomery Multiplication
MATLAB-and-Verilog-codes
- there are 5 files. the first two codes are written in Matlab as m-files in control system design to show step responses. in contrast, the final three codes are written in verilog ( Quartus II) used in Altera one of them for BCD adder and the other fo
adder
- 详细介绍多种方法实现加法器，有行为级，结构级，数据流级等，适合初学者迅速掌握Verilog语言。-Different methods of achieving adder is divided into behavioral, structural level, the data flow level, etc., suitable for beginners to quickly master the Verilog programming language
adder
- adder for verilog for complex addition etc
Piplined_RCA
- Pipelined Ripple Carry Adder verilog source file
ADDR
- 8位全加器，包括半加器verilog文件，全加器verilog文件，8位全加器verilog文件，和8位全加器测试testbench文件-8 full adder, including half adder, full adder Verilog file, Verilog file, 8 full adder Verilog files, and 8 full adder test testbench file
32-bit-carry-look-ahead-adder
- This file contains Verilog codes
Ripple-carry-adder
- Ripple carry adder using system verilog
full_adder
- a full adder verilog source created by two half adder
VERILOG-Simulation
- This VERILOG simulation example shows a 16 bit group ripple adder circuit for FPGA. The netlabel is used to split 16 bit bus to four 4 bit bus and connect them to four 4 bit adder. The result is joined to a 16 bit bus using netlabel. The Simulation c
16Bit-Group-Ripple-Adder
- Verilog Testbench for 16Bit Group Ripple Adder
Area-Delay-Power-Efficient-Carry-Select-Adder-usi
- Implementation of IEEE 2015 paper for Area–Delay–Power Efficient Carry-Select Adder using VLSI verilog .The code tested by modelsim and also main program is test.v . If have any trouble mail to anandg.embedd@gmail.com-Implementation of IEEE 2015 pape
cla_16bit
- verilog 16bit carry lookahead adder-verilog 16bit carry lookahead adder
adder
- 能够实现单精度浮点加法运算。输入引脚有：第一运算数，第二运算数，复位信号，时钟信号。输出信号有：运算结果，运算完成标志。(To achieve a single precision floating-point addition operations)
BKA264
- Verilog - Brent-Kung Adder 32-bits
CSA464
- Verilog - Combinational part of Carry-Save adder, 4 operands 64-bits
HCA464
- Verilog - Descr iption of a 4 operand 64-bit Hans-Carlson adder
add
- verilog实现的完整的加法器，包括测试文件等(Verilog implements a complete adder, including test files)
BCDadder
- cource code for BCD adder in verilog language
常用加法器设计
- 采用Verilog设计的几种常用加法器。(several adder designed by Verilog)