搜索资源列表
AlteraSdramIP
- Altera Sdram IP 源码.rar-Altera Sdram IP source code. Rar
AlteraFPGAboard
- Altera的FPGA开发板原理图汇集-Altera' s FPGA development board schematics together .....
9927416JpegDecoder
- altera nios处理器快速入门，对研究NIOS的人员很有帮助-altera nios processor, quick start, the staff very helpful for research NIOS
AlteraFPGA
- quartus II 软件入门和进阶，是《ALtera fpga_cpld 设计》（基础篇）-quartus II software, introductory and advanced, is " ALtera fpga_cpld design" (Basics)
lcd2tft
- convert lcd 4 bits to tft 16 bits.Writen verilog,Altera Quartus.
LED
- 本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA 公司的 Cyclone II 系列 FPGA 为数字平台，将微处理器、Avalon 总线、LED 点阵扫描控制器、存储器和人机接口控制器等硬件设备集中在一片 FPGA 上，利用片内硬件来实现 LED 点阵的带地址扫描，降低系统总功耗和简化 CPU 编程的同时，提高了系统的精确度、稳定性和抗干扰性能。-This design used the Nios II embedded processor based o
diglab3
- lcd test on the altera de2 board with switches and leds
asynchronous_fifo
- Fully asynchronous fifo for Altera devices.
timer
- AHDL parametrized timer - for Altera Quartus compiler only-AHDL parametrized timer- for Altera Quartus compiler only
de2_clock
- de2_clock on altera de2 board
video_encoder_board_att
- This the artwork for a board that connects a video encoder chip to a Altera DE1 board (or any other) via a IDE cable-This is the artwork for a board that connects a video encoder chip to a Altera DE1 board (or any other) via a IDE cable
altera_up_avalon_character_lcd
- LCD例程 altera官方Verilog代码 详尽简单实用-LCD routines altera official Verilog code is simple and practical details
SOPC_UART
- altera公司的ep1c240c8n，串口调试程序vhdl\nios ii8.0代码等-altera company ep1c240c8n, serial debugger vhdl \ nios ii8.0 code. .
pdn_tool_v1_0
- altera 的电磁分析工具，非常有用的。讲解详实具体-altera electromagnetic analysis tool, very useful. To explain the specific detailed
ALTERA_JTAG
- Altera 的下载线官方资料，可以制作JTAG和AS模式的下载线-Altera download cable official information, you can create JTAG and AS modes download cable
vhdl_sram_ctrl
- Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus -Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus II
basedonFPGALCD
- 基于FPGA的LCD接口程序代码，可以在xilinx或altera开发板运行-FPGA-based LCD interface program code, you can run the xilinx or altera Development Board
lcd_drv
- lcd driver 16x2 to drive lcd dispaly on altera de2 board
fpga_memory_rev_1_0
- Various memories for Xilinx and Altera FPGA devices. Single-port and Dual-port versions with various numbers of read and write ports. Bundle also includes read-first and write-first varieties with sync and async clocks. All memory compo
altera_up_avalon_sd_card_interface_91
- 修改后的Altera大学计划IP Core，可用于QII9.1及9.1SP1-Revised Altera University Program IP Core, can be used for QII9.1 and 9.1SP1