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并口的CPLD烧录线，通过跳线支持三大厂家的CPLD/FPGA(Altera,Xilinx,Lattice)
- 并口的CPLD烧录线，通过跳线支持三大厂家(Altera,Xilinx,Lattice)的CPLD/FPGA烧录,附有电路图与Verilog HDL文档.使用的芯片为XC9572XL-VQ64
基于Altera FPGACPLD的电子系统设计及工程实践
- 基于Altera FPGACPLD的电子系统设计及工程实践
altera sdram controller
- altera sdram controller vhdl
Altera IP Core
- 15 Altera IP Core
ug_alt_ufm.rar
- ALTERA公司的MAXⅡ系列CPLD的内部flash使用教程，内容很详细，图文并茂，英文版。,ALTERA s MAX Ⅱ series CPLD to use the internal flash tutorial is very detailed, with illustrations in English.
altera_epm1270_MAX.rar
- 一个ALTERA公司EPM1270 cpld的实验板原理图，其中有PCI接口电路，PDF格式,A ALTERA Corporation EPM1270 cpld schematic diagram of the experimental board, including PCI interface circuit, PDF format
vga_moving_pixel.rar
- 该项目在VGA显示器上显示一个移动的光点，并且光点的颜色还可以改变。使用VerilogHDL 语言编写，在Altera公司的QuartusII开发环境下验证通过。,The project in the VGA display to show a moving spot, and spot colors can be changed also. VerilogHDL language used in Altera' s development environment QuartusII ve
vga_hex_disp.rar
- 该项目可在VGA显示器上显示ＲＡＭ或ＲＯＭ中的十六进制数据，使用ＶｅｒｉｌｏｇＨＤＬ语言编写，在ＱｕａｒｔｕｓＩＩ开发环境下验证。,The Project displays the content of memory cells in the form of hexadecimal numbers. It uses RAM and ROM memory modules available through special functions. This is why before compilin
AteralIP.rar
- Altera IP核8B10B编码器的完整设计流程包括Altera IP的定制、仿真和实现的全过程,Altera IP core of the integrity of the 8B10B encoder design process, including the Altera IP customization, simulation and realization of the whole process of
B.rar
- altera usb下载线原理图和cpld程序,altera usb download cable schematics and procedures cpld
tftlcd.zip
- TFT LCD controller verilog code using ALTERA FPGA.,TFT LCD controller verilog code using ALTERA FPGA.
altera_avr_down.rar
- 可用于ALTERA 的CPLD和AVR 单片机的并口下载器的电路原理图和PCB图（PROTEL DXP）,经实验可直接使用。,ALTERA the CPLD can be used and the AVR MCU' s parallel port to download schematic and PCB circuit diagram, can be directly used by the experiment.
alteralvds.rar
- 基于altera系列芯片lvds接口的fpga设计 verilog源码,Series altera-based chip interface lvds source fpga design verilog
68013_USB_blaster
- 采用CY7C68013制作ALTERA USB Blaster的详细资料-Make a ALTERA USB Blaster yourself by CY7C68013.
Altera_DDR_controller_core
- Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
Crack_QII_11.1_Window11.1
- altera quartus 11.1破解版-altera quartus 11.1破解版工具
IPcore
- 基于EP3C25的Altera SDI IP核的使用-EP3C25 Altera SDI IP
SDRAM_ipcore_
- Altera SDRAM ip核详解-Altera SDRAM ip nuclear Detailed
mem32_to_pcitarget_verilog
- This design example shows how to implement interface between 32-bit pci target Altera megafunction instantiation and a 32-bit synchronous memory
FFT_verilog
- verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to