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signal_cpu_sort
- Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_ME
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
alu
- this is source code in verilog for arithmatic logic unit for RISC cpu
m.e-lab
- vhdl verilog code for alu operation pll,biy sliced processor
SRC
- 流水线cpu 顶层模块verilog源代码，和ALU子模块源代码-Pipelined cpu top-level module verilog source code, and the ALU sub-module source code
SourceCode
- That s a bunch of ALU control code for MIPS pipelined in Verilog!
alu
- It is 32 bit ALU code in Verilog HDL programming Language
VeriRISC_CPU_Verilog
- Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo
ALU
- ALU，两种类型的verilog源代码，包括测试代码，原创。-ALU, two types of verilog source code, including test code, originality.
day8_alu_design
- this verilog code for designing ALU in fpga.-this is verilog code for designing ALU in fpga.
CPU_Verilog
- 此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)