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simple clock
- A simple clock with VHDL code.
基于verilog HDL语言的电子钟
- 基于verilog HDL语言的电子钟,多功能电子时钟,Verilog HDL language-based electronic bell, electronic multi-function clock
daima.用VHDL语言设计一个数字秒表
- 用VHDL语言设计一个数字秒表: 1、 秒表的计时范围是0秒~59分59.99秒,显示的最长时间为59分59秒。 2、 计时精度为10MS。 3、 复位开关可以随时使用,按下一次复位开关,计时器清零。 4、 具有开始/停止功能,按一下开关,计时器开始计时,再按一下,停止计时。系统设计分为几大部分,包括控制模块、时基分频模块、计时模块和显示模块等。其中,计时模块有分为六进制和十进制计时器。计时是对标准时钟脉冲计数。计数器由四个十进制计数器和两个六进制计数器构成,其中毫秒位、十毫秒位、秒位和
用 vhdl 设计含异步清零和同步时钟使能
- 用 vhdl 设计含异步清零和同步时钟使能的十进制加法计数器。再用 vhdl 设计含异步清零和同步时钟使能的十进制加减可控计数器。 -With vhdl design with asynchronous clear and synchronous clock enable decimal up counter. Vhdl design and then synchronize with asynchronous clear and clock enable control counter
基于fpga的多功能电子钟的设计
- 基于fpga的多功能电子钟的设计非常使用希望对大家有帮助啊,FPGA-based multi-functional electronic clock design to use would like to help everyone ah
parell_to_serial.rar
- 该模块主要完成并串转换功能。其中system_clk是输入并行时钟的频率,它是串行时钟serial_clk的八倍。byte_data_en是输入并行数据使能信号,byte_data是输入并行数据。serial_data是转换后的串行数据,bit_data_enable是串行数据有效信号。,The module main is completed and the string conversion functions. System_clk which is an input parallel c
vhdl_clock.rar
- VHDL数字钟设计程序 设计要求 基本要求: 1、24小时计数显示; 2、具有校时功能(时,分) ; 附加要求: 1、实现闹钟功能(定时,闹响);,VHDL digital clock design process design requirements for the basic requirements: 1,24 hours count display 2, with a school function (hours, minutes) additio
LPT.rar
- 实现开漏输出的并口,支持3.3V或5V,支持FPGA 的PS 配置功能。8位配置数据 自动移位输出,输入时钟24MHz,产生1MHz配置时钟。8位CPU数据总线接口, 11位地址总线。支持IO 的置位清除功能。,The realization of open-drain output of the parallel port, support 3.3V or 5V, support for FPGA configuration of the PS function. 8-bit config
sd_reader.rar
- SD卡读卡器模块的VHDL及软件驱动代码,可作为外设挂接在Avalon总线上。支持以SD模式、4线模式读取。在24MHz时钟驱动下读取速率可达8MByte/s,SD card reader module and software drivers VHDL code, can be articulated as a peripheral bus in Avalon. To support the SD model, 4-wire mode read. Driven by the 24MHz clo
FPQ.rar
- 分频器的vhdl描述,在源代码中完成对时钟信号CLK的2分频,4分频,8分频,16分频,Divider vhdl descr iption of the source code at the completion of the CLK clock signal frequency of 2 hours, 4 minutes frequency, frequency of 8 hours, 16 minutes frequency
liuVHDL.rar
- 一种基于状态机设计的串并行转换电路,将LTC1196(ADC)的串行输出数据转换成并行数据的转换电路, ADC的时钟由转换电路提供,,Design a state machine based on parallel conversion circuit of the series will be LTC1196 (ADC) output of the serial data into parallel data conversion circuit, ADC clock provided by
shuzi.rar
- 数字电子钟设计,整点报时,时分秒分模块设计,另附实验报告和实验结果,内容详细不容错过,The design of digital electronic clock, the whole point of time when minutes and seconds sub-module design, an additional test reports and laboratory test results, the details not to be missed
FPGA_nCLK.rar
- VHDL语言的高频时钟分频模块。一种新的分频器实现方法。,VHDL language at the high-frequency clock frequency modules. Divider to achieve a new method.
clock.rar
- 具有流水灯报点的数字钟实验 含有报告,用VHDL编写,Water at point of light with the number of minutes containing the report of the experiment, prepared by VHDL
vgaclock.rar
- vga显示的数字时钟,用mif文件实现,用以大家学习交流,vga display digital clock, with the realization of mif file for them to learn from the exchange of
clock.rar
- 用vhdl实现的多功能时钟,有整点响铃,秒表等多种功能,Use VHDL to achieve multi-functional clock, there is the whole point of the bell to ring, a variety of functions such as stopwatch
jishuqi.rar
- 描述的是一个带有异步复位和同步时钟使能的十进制加法计算器,,With reset and clock enable decimal calculator
clock.rar
- VHDL编写的,实现电子手表功能,硬件语言描写,定时非常准确,VHDL prepared, electronic watches, functions, hardware descr iption languages, timing is very accurate
zz.rar
- 键控加/减计数器,将20MHz系统时钟经分频器后可得到5M、1M、100K、10K、5K、1K、10Hz、1Hz ,Keying increase/decrease counter to 20MHz system clock by the divider available after 5M, 1M, 100K, 10K, 5K, 1K, 10Hz, 1Hz
baseband_verilog.rar
- verilog实现的基带信号编码,整个系统分为六个模块,分别为:时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器,verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum m