搜索资源列表
EDA
- 数字钟的实现 FPGA上运行 VHDL编写-Digital clock running on the FPGA to achieve the preparation of VHDL
alarm_system
- 电子闹钟：基于fpga的电子闹钟设计，采用模块化方式-Electronic alarm: FPGA-based electronic alarm clock design, modular approach
shizhong
- 用vhdl语言描述时钟的功能，并通过七段译码显示输出。-VHDL language used to describe the function of the clock and through the Seven-Segment display decoder output.
any_div_freq
- 可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.-Can be arbitrary points on the input clock frequency (integer or decimal), with complete Quartus II project document.
shuzizhong
- 可预置数字钟，用VHDL语言编写，LED显示，普通数字钟表。-Digital clock can be preset using VHDL language, LED display, an ordinary digital watch.
uart
- 用VHDL实现的一个uart控制器，输入时钟为33M-Use VHDL to achieve a UART controller, input clock for the 33M
watch
- 功能更强大的数字时钟,有年份,月,日,时,分,秒和星期,可以调校-More powerful digital clock, there are years, months, days, hours, minutes, seconds and weeks, you can adjust the
PCR
- 本程序是在传输流传输过程中对节目时钟字段进行检测与修改,采用Verilog HDL 语言进行编程。-This procedure is in the transport stream during transmission of program the clock to carry out field testing and modification, using Verilog HDL language programming.
clock
- 多功能电子时钟，具有时间显示，时间调整等功能。-Multi-function electronic clocks, time display, time adjustment functions.
digitalclock.vhd
- 实现电子钟的功能，使用VHDL编程语言，调试已经通过-Electronic clock function, the use of VHDL programming language, debugging has been passed
divider
- 该模块为分频器，将1KHZ的时钟频率分频成每分钟一次的时钟频率 事实上，该源码可以实现任意整数的分频，主要让N的值设置好相应的数字-The module for the divider, the clock frequency 1KHz frequency per minute into the first clock frequency In fact, the source can be any integer frequency, mainly to allow the value o
dianzizhongfangzhen
- 8.20 电子时钟VHDL程序与仿真 为初学者提供很好的范例-8.20 electronic clock VHDL program for beginners and simulation provides an excellent example of
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
vhdl_miaobiao
- 用vhdl实现秒表的功能，具有秒表功能,有分、秒显示，后期可以自己添加闹钟的模块。 -Use VHDL to achieve the functions of a stopwatch with a stopwatch function, who, seconds indicates that the latter can add their own alarm clock module.
timer
- vhdl代码：电子时钟VHDL程序与仿真！初学fpga者可以参考参考！！比较简单-VHDL code: electronic clock and simulation of VHDL procedures! FPGA beginner who can refer to reference! ! Relatively simple
ssz
- 数字钟，用VHDL写的各个模块，顶层用图形编辑，在实验箱上完全通过-Digital clock, using VHDL written by various modules, top-level graphics editing, in the experimental box completely through
RS232_pro
- RS232 verilog coding 全参数化设计 可以自己设定波特率 时钟频率等 完全FPGA实现调通-RS232 verilog coding the entire parametric design can set the baud rate clock frequency of FPGA to achieve complete transfer pass
clock
- 电子闹钟 clk： 标准时钟信号，本例中，其频率为4Hz； clk_1k： 产生闹铃音、报时音的时钟信号，本例中其频率为1024Hz； mode： 功能控制信号； 为0：计时功能； 为1：闹钟功能； 为2：手动校时功能； turn： 接按键，在手动校时功能时，选择是调整小时，还是分钟； 若长时间按住该键，还可使秒信号清零，用于精确调时； change： 接按键，手动调整时，每按一次，计数器加1； 如果长按，则连续快速加1，用于快速调时和定时； hour,
shizhong
- 简单的VB时钟控件操作，对于刚学习VB.net的人很有帮助-VB simple clock control operation, for people just learning VB.net helpful
VHDL
- 数字钟的设计，有时，分，秒，置数等功能。-Digital clock design, sometimes, minutes and seconds, buy a few functions.