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cnt24_t
- 这是二十四进制计数器的源程序，有需要的同学可以参照一下！-This is 24 hexadecimal counter source, needy students can refer to you!
cnt24
- 24进制的VHDL程序，适合EDA初学者使用的基础实验-24 into the system, suitable for beginners program VHDL EDA of fundamental experiment using
cnt24
- 24进制计数器，实现了电子时钟小时位的24进制计数-24 hex counter
jinwang
- 4位二进制计数器 基于quartus2程序-module CNT24(CLK,Q) output [3:0] Q input CLK reg [3:0] Q1 always @(posedge CLK) begin Q1<=Q1+1 end assign Q=Q1 endmodule
cnt24
- VHDL24秒篮球倒计时,VHDL编写，实现23到0计数。quartues ii 9.1编写的。-VHDL24 sec basketball countdown, written in VHDL, to achieve 23 to 0 count. Quartues written in II 9.1.