搜索资源列表
FPGA_CPLD
- FPGA CPLD入门教程 对于初学者很实用-FPGA CPLD Getting Started tutorial is very useful for beginners
s3esk_startup
- 利用kcpsm3控制lcd显示 平台:ise 10.1, picoblaze, Spartan3e 开发板 说明:综合按键和lcd、led的功能,思想简单,需要新技术,适合想在fpga方面深造的人。-using kcpsm3 for lcd display platform: ise 10.1, picoblaze, Spartan-3E FPGA Starter Kit Board comment: involve lcd/led/switch, simple mind bu
PIC10_RISC_Verilog
- The PIC10-compatible microcontroller core was implemented as part of a client project where a small PIC-compatible microprocessor IP Core was needed to be integrated into a CPLD or FPGA. This allowed extremely fast but yet simple firmware programming
Verilog
- VERILOG语言的学习,更好的运用CPLD,FPGA-VERILOG language learning, better use of CPLD, FPGA
vhdl_sram_ctrl
- Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus -Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus II
fpgacpld
- FPGA/CPLD开发教程,可以作为入门级学习资料。-The PDF file of CPLD,
STOPWATCH
- 是基于FPGA/CPLD的跑表程序,可以存储记录多个运动员的跑步时间,是利用VHDL语言编写的,可以有助于学习EDA技术,可以参考学习,可以帮助你完成VHDL语言的课程设计。-Is based on FPGA/CPLD s stopwatch program, many athletes can store records of running time, is the use of VHDL language, and can help to learn EDA, can refer to t
VHDLbaseddesignofmusicplayer
- 在EDA开发工具Quartus II 6.0平台上,采用VHDL语言层次化和模块化的设计方法,通过音符编码的设计思想,预先定制乐曲,实现动态显示乐曲演奏电路的设计,并在此基础上,基于同一原理,使此电路同时具备了简易电子琴的功能,使基于CPLD/FPGA芯片的乐曲播放数字电路得到了更好的优化,提高了设计的灵活性和可扩展性。- Based on the QuartusII-the EDA development tool, this design has adopted the method of
51fpga
- 51单片机 IP核 FPGA CPLD 基于EDA技术的兼容MCS_51单片机IP核设计- FPGA CPLD
FPGAclock
- FPGA CPLD重要设计思想及工程应用时钟设计-FPGA CPLD design and engineering major clock design
dac8552
- 使用Verilog HDL语言编写的实现DAC8552的时序程序,单片机总线与CPLD/FPGA通信,单片机负责控制送数实现功能。-Use Verilog HDL language DAC8552 realization of temporal procedures, SCM bus and CPLD/FPGA communication, SCM control to send several functions.
FPGA_Verilog_LCD_12864
- 使用Verilog HDL语言编写的驱动LCD12864的时序,可以直接用FPGA/CPLD驱动LCD12864了。-Using Verilog HDL language driver LCD12864 timing, can be directly used FPGA/CPLD driver LCD12864 the.
CPLD
- FPGA与CPLD之间通过串口通信的程序,波特率为9600。-FPGA and CPLD via the serial port communication program, the baud rate to 9600.
modesim
- 讲述使用modelsim进行验证,使用verilogHDL语言进行建模。其中还包括一个讲述怎样用verilog语言编写测试台的详细文档,对fpga cpld设计的后期验证有很大的帮助。-About the use modelsim for authentication, use verilogHDL language modeling. It also includes a focus on how to use verilog test bench written a detailed doc
AlteraFPGACPLDcoder
- Altera FPGA/CPLD设计(基础篇)随书代码-Altera FPGA/CPLD design (fundamental) with the code book
AlteraFPGACPLDcoder2
- Altera FPGA/CPLD设计(高级篇)随书代码-Altera FPGA/CPLD Design (Senior Posts) With the written code
Altera_FPGA_CPLD_Designing(Advanced)
- Altera FPGA_CPLD设计(高级篇) Altera FPGA/CPLD学习的优秀参考书-Altera_FPGA_CPLD_Designing(Advanced)
Max_Plus_II-_tutorial
- Max+plusII(或写成Maxplus2,或MP2) 是Altera公司推出的的第三代PLD开发系统(Altera第四代PLD开发系统被称为:QuartusII,主要用于设计新器件和大规模CPLD/FPGA).使用MAX+PLUSII的设计者不需精通器件内部的复杂结构。设计者可以用自己熟悉的设计工具(如原理图输入或硬件描述语言)建立设计,MAX+PLUSII把这些设计转自动换成最终所需的格式。其设计速度非常快。Maxplus2被公认为是最易使用,人机界面最友善的PLD开发软件,特别适合初学者
CPLD_FPGA
- 基于CPLD/FPGA的数字通信系统建模与设计,里面讲述了通信系统的VHDL建模和各种基本电路的建模与设计,在通信原理课程设计中一般会用到!-Based on CPLD/FPGA Digital Communication System Modeling and Design, which describes VHDL modeling of communication systems and a variety of basic circuit modeling and design, pri
FPGA-CPLD
- FPGA-CPLD开发教程.rar 开发fpga必看的书籍 可以参考着开发 作为不时之需-FPGA-CPLD Development tutorial. Rar fpga development can refer to the books must see development as a rainy day