搜索资源列表
8080cpu
- this code for cpu 8080 design -this is code for cpu 8080 design
testbenchcpu8080
- this is code testbench cpu -this is code testbench cpu 8080
ALU
- 这是一个用vhdl语言实现的比较完整的ALU,可以用作其他cPU设计的部件-This is a vhdl language used to achieve complete ALU, can be used for other design components cPU
Jh_cpu
- Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin way.-This VHDl code can provide a total clear and detail process to create a basic function risc cpu.
POCREPORT
- 为充分利用CPU的运行效率，采用中断功能设计并行输入输出接口，以达到缓解CPU高速运行速度与外设低速缓冲间的矛盾。-To take full advantage of the efficiency of CPU operation, interruption of functional design using parallel input-output interface, in order to alleviate the CPU speed and high-speed periphera
first_cpu
- nios ii cpu核，包含通用IO口、sdram、flash、uart-nios ii cpu、genernal io port、sdram、falsh、uart
computer4
- 基于FPGA的CPU核及其虚拟平台的设计与实现-FPGA-based CPU core and its virtual platform design and implementation of
POC
- 东南大学学生数字系统设计实验：用VHDL语言编写Printer与CPU互连的接口程序-Southeast University students in the experimental digital system design: VHDL language with Printer and CPU interface interconnection procedures
dianhuanyuanchengkongzhi
- 电话智能遥控器主要包括电话振铃检测电路，电话自动摘机和挂机电路，DTMF信号解码电路，语音提示急电路，音频放大电路，以及控制心脏CPU电路-Telephone remote control including smart phones ringing detection circuit, telephone and hang up automatically pick circuit, DTMF signal decoding circuit, urgent voice circuits, au
8051-core
- mcu8051 CPU FPGA VHDL software
soc-gr0040-010309
- xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
lariviere2008uclinux
- xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
CPU
- Xilinx Modelsim下制作的处理器设计以及添加了外部接口处理。-Xilinx Modelsim produced the design of the processor, and add an external interface.
timer
- 计时器的Verilog描述 CPU设计者可以借鉴 -Verilog decription of the timer in processors
cpu16
- 实现一个16位CPU。该CPU使用精减指令集，是一个五段流水线的结构。包括取指令(IF)、读寄存器(RD)、运算器(ALU)、内存读写(MEM)和写回(WB)。-The realization of a 16-bit CPU. Streamline the use of the CPU instruction set is a structure of five lines. Including fetch (IF), register read (RD), arithmetic logic u
CPU_Architecture
- Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common netw
cpu_eightbit
- vhdl implementation of an eight bit cpu
uart
- 用ALTERA的芯片做的多串口代码，内部做了3个通用串口，适合51 ARM等CPU，有完整的ALTERA工程和仿真波形-uart FOR ALTERA
S7_PS2_RS232
- 利用cpld作为cpu控制器将ps2中取得按键值通过串口传送给pc机-cpld verilog ps2 UART
pipeline
- 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time