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C5GX开发板原理图和PCB
- Altera_Cyclone V GX FPGA Development Kit原理图PCB 供参考(Altera_Cyclone V GX FPGA Development Kit_sch_pcb)
RGMII_RECEIVER
- This module converts 4 bit DDR RGMII flow to 8 bit SDR flow, proved on Altera Cyclone 3 devices.
LED_test
- Altera Cyclne IV example for Quartus
C4E6-K SCHv2
- Altera board shhematics
elevator
- 八层电梯，有密码开关，警报开关，quartusⅡ综合，cycloneⅤ的板子(There are password switches, alarm switches, and eight layers of elevator display, Quartus II synthesis, cyclone V board.)
NIOS-II常用函数详解
- Nios II系列软核处理器是Altera的第二代FPGA嵌入式处理器，其性能超过200DMIPS，。Altera的Stratix 、Stratix GX、 Stratix II和 Cyclone系列FPGA全面支持Nios II处理器，以后推出的FPGA器件也将支持Nios II。(The Nios II family of soft core processors is the second generation of Altera's FPGA embedded processor tha
04_uart_test
- 基于FPGA的串口通信实验，用的是黑金板子CYCLONE IV(FPGA UART test code,simple and easy to study,good)
text seven
- VGA彩条信号显示器设计 设计并调试好一个VGA彩条信号发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera CycloneII系列的 EP2C5T144C8 FPGA。(A VGA color bar signal generator is designed and debugged, and an EDA experimental development system is used (the model of the experimental chip to be use