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DDR控制器
- 不错很详细
AVR位操作通用支持库，傻孩子编写
- AVR位操作通用支持库，傻孩子编写，提供了针对PORT的位操作和部分PIN、DDR的位操作。
ddr_sdram
- ddr_sdram的控制程序，希望有用。
ddr_sdram_controller_vhdl.rar
- DDR SDRAM控制器的VHDL代码已经测试,DDR SDRAM controller VHDL code
DDRSDRAM_controller
- ddr sdram控制器，lattice器件的参考设计，比较详细-ddr sdram controller, lattice components of the reference design, very detailed
sram
- sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation
Crack_QII81_FULL_License
- quartus 8.1 ipcore lic,包含ddr、ddr2、fir、nco-quartus 8.1 ipcore lic, with ddr, ddr2, fir, nco
DDR_FLASH_VHDL_Verilog
- FPGA DDR 外部RAM 读写的verilog代码，以及FLASH的vhdl代码-DDR SRAM READ AND WRITE VERILOG CODE ,FLASH VHDL CODE ,FPGA
omapl138
- OMAPL138的GEL和DEMO例程，方便快速进行项目的开发-OMAPL138 of GEL and DEMO routines to facilitate rapid development of the project
ddr_ddr2_sdram9.0
- altera 公司提供的ddr_ddr2_sdram9.0，DDR2 SDRAM 源代码-altera provided ddr_ddr2_sdram9.0, DDR2 SDRAM source code
simulator
- 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is
EP3C120
- EP3C120的官方开发板原理图，cyclone iii 系列最大的FPGA.-EP3C120s official development board schematics, cyclone iii series of the largest FPGA.
1
- PCIE 与DDR的接口范例，由altera提供-PCIE and the DDR interface examples provided by the altera
DDR_SPEC
- DDRSRAM 由于经常看到，经常用到，所以还是大家下载下来看看吧！-DDRSRAM often see as a result, frequently used, so we downloaded it to see!
smo
- 一套DDR OL 游戏源码.也就是所谓的SMO.内置SQL 及其完善的源码 可以用作2次开发等-A set of game-source DDR OL. That is, the so-called SMO. Built-in SQL and its sound source can be used as 2 times the development of
DaVinciEVM_Schematic
- DaVinciEVM,TI 达分奇原装板原理图，主要有DDR，ETHNET，HDD，POWER等设计图，内部丰富，结构完整，是设计者的参考资料-DaVinciEVM, TI Tatsu at odd original board schematic, there are DDR, ETHNET, HDD, POWER, such as design drawings, internal rich structural integrity, are the designers of referen
LVDS_DDR_List_FPGA2
- FPGA芯片与ADI公司的AD9779之间的通信，总共有四个通道，68对LVDS,采样时钟是122.88MHz-FPGA chips ADI' s AD9779 and communication between, a total of four channels, 68 pairs of LVDS, the sampling clock is 122.88MHz
Peercast
- peercast带注释的，方便大家研究源程序，这是我师兄的心血-peercast