搜索资源列表
u26a_spice
- ddr2控制器一些源码，控制时序及怎样通过嵌入式cpu来进行控制的实例-ddr2 Controller some source code, and how to control the timing of embedded cpu passed to the control of the examples
DDR2-SDRAM-REPORT
- this is a wor file for ddr2 question that give introduction
Spartan3-FPGA--DDR2-SDRAM
- FPGA学习资料，入门级掌握资料，ddr2内存-Spartan-3 FPGA 的 DDR2 SDRAM
ddr2
- leon3系统中ddr2控制器的相关代码（还包包括存储器的仿真模型），该控制器可以与amba2.0的ahb总线相连，机构比较复杂，代码量很大-ddr2 controller code (package includes the memory of the simulation model) leon3 system, the controller can with amba2.0 the ahb bus connected to more complex institutions, the am
ddr2
- 基于OMAP-L138 的DDR2 存储 源代码-DDR2 memory source code based on the OMAP-L138
ddr2
- 基于xilinx spartan -3A DSP的ddr2控制器-Based on the Xilinx Spartan-3A DSP DDR2 controller
OMAP-L138-DDR2-TEST
- 基于OMAP-L138的DDR2存储测试源代码-TESTING CODE FOR OMAP-L138 DDR2
ddr2
- xilinx ddr2 mig核读写控制 verilog -xilinx mig write and read timing
DDR2 控制程序
- DDR2接口控制程序，很适合初学者学习与应用
XILINX DDR2
- xilinx ddr2 ip核的verilog例子
ddr2
- OMAP-L138芯片的ddr2测试例程，内涵源代码-OMAP-L138 chip ddr2 test routines, content source code
Hardware-Layout-Design-for-DDR2
- ddr2的硬件布线设计学习资料-hardware design for ddr2，verilog
DDR2-design-out-of-fpga
- FPGA外部的ddr2设计的相关学习资料-off-fpga，ddr design
S3C2416-DDR2-MMU-IRQ-Jlink
- IAR中裸奔S3C2416的例子(DDR2+MMU+中断+J-link）-IAR examples in the streaking S3C2416 (DDR2+MMU+ interrupt+J-link)
DDR2-verilog
- ddr2的Verilog代码，包括时序控制，数据读取，利用verilog编写的ddr2控制器，在spartan6板子上得以验证，成功实现了FPGA与DDR2的通信。-ddr2 of Verilog code, including timing control, data is read using verilog prepared ddr2 controller board on spartan6 be verified, the successful implementation of the
ddr2
- ddr2 仿真模型，适应于modelsim 仿真，内涵仿真核源码-ddr2 simulation model adapted to the modelsim simulation, simulation connotation nuclear source
t2_hpc
- DDR2的控制器设计，完成功能的验证，以及仿真测试，(DDR2 controller design, complete function verification, and simulation test,)
ddr2_module
- 设计的DDR2的verilog代码.改代码实现读取DDR2的数据。(the code for DDR2.It is used for reading the data of DDR2)
DDR2_Control
- 参考例程之Verilog之实现DDR2时序控制实现，ISE开发平台完整工程(Implementation of DDR2 timing control implementation of reference routine Verilog, complete engineering of ISE development platform)
DDR2_Control
- 本人用verilog编写的DDR2控制器，经测试可用。(I am prepared to use verilog DDR2 controller, the test is available.)