搜索资源列表
DDR3L_H5TC4G4(8_6)3AFR
- The H5TC4G43AFR-xxA, H5TC4G83AFR-xxA and H5TC4G63AFR-xxA are a 4Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operatio
BeagleBone-Black-master
- 狗板子的原理图，应用了三星公司的DDR3存储器，是一款不错的板子，具有参考价值-Schematic dog board, the application of Samsung s DDR3 memory, is a good board, a reference value
SIV_ALTMEMPHY_DDR3
- ddr3 interface demo,
DDR3_Test
- ddr3基于ISE的测试仿真工程文件，配合开发板使用，适合ddr3入门者-ddr3 sim-documents for new learners
DDR3_controller
- DDR3的控制器程序，可烧录到FPGA中对内存进行读写，可在该代码上修改用于其他场合。-DDR3 controller program, are programmed into the FPGA, memory read and write, you can modify the code used on other occasions.
mcb_traffic_gen
- 本文档为ddr3的控制器，可以实现DDR3的读写操作。-This document is ddr3 controller, DDR3 can achieve read and write operations.
MT9M001
- FPGA驱动MT9M001的verilog代码，里面还有ddr3部分将图像数据进行存储，lcd进行图像显示，里面的摄像头驱动部分很详细，大家可以多研习研习-Verilog driver MT9M001 code, which is also the DDR3 image data storage, LCD display, which drives the part is very detailed, we can learn more
MB_DDR3
- 利用Spartan6的软核MicroBlaze来测试读写DDR3的历程。利用官方提供的函数以及实时查看内存来验证DDR3的读写是否成功-Use of Spartan soft-core MicroBlaze 6 to test reading and writing DDR3 course. The use of official functions and real-time view to validate DDR3 memory read and write was successful
mig_7series_v1_9
- DDR3控制器源码，针对XilinxFPGA的DDR3控制器的源码，已经验证通过。-DDR3 Controller，complete DDR3 controll，have pass verificaion.
DDR3_128M16bit_2Port64bit
- Xilinx spartan6 DDR3驱动，编程语言Verilog，基于MCB硬核。-Xilinx spartan6 DDR3 driver based on MCB ip core,coding by verilog.
sdram_test
- 在vivado中用于测试SDRAM，DDR3学习比较有帮助-the testbench for ddr3
ddr3_verilog
- DDR3读写在FPGA上的实现代码，经测试通过-DDR3 read and write FPGA implementation of the code, the test passed
DDR_TEST
- 基于xc65slx16的ise 14.7 DDR3测试模版，经过验证，可供fpga开发参考学习，也可作为开发模版。-Based on xc65slx16 ise 14.7 DDR3 test template, validated and can be used for reference in the fpga development study, also can be used as a template development.
I.MX6DQSDL-DDR3-Script-Aid-V0.10
- 飞思卡尔平台imx6 DDR配置参数配置工具。-Freescale platform imx6 DDR configuration parameter configuration tool.
21_flash_ddr_lcd
- flash与DDR3的程序，verilogHDL语言描述的程序-flash and ddr3 verilogHDL soft
11_ddr3_test
- ddr3的操作程序，用Veriloghdl写的FPGA程序-ddr3 veirloghdl operater xinlinx FPGA
DDR3_SO_DIMM
- 为FPGAddr3的IP核程序，实现ddr3芯片的读写操作-FPGAddr3 for the IP kernel program, the realization of DDR3 chip read and write operations
axi_master
- DDR3 控制器，axi4_full 模式， burst长度为16，应用于xilinx平台。-DDR3 interface controller， axi4_full working mode with burst length 16, can operate on the xilinx platform.
DDR3_SDRAM
- ddr3 sdram 功能测试。读写测试还有自刷新测试，测试通过。-ddr3 sdram test,write and read ,aoturefresh
FETIMX6UL
- IMX6UL 开发板原理图，带DDR3,NAND FLASH,ETH,UART,USB等丰富的外部接口。(SCH OF IMX6UL DEMO BOARD)