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dds_mul
- 简单的多周期dds的verilog编程,出来一个正弦波,可任意改变频率字-Simple multi-cycle dds verilog programming, out of a sine wave, the frequency can be arbitrarily changed words
dds
- verilog编写的dds发生器,修改频率字可改频率-dds in verilog
DDS
- 用verilog语言实现,DDS信号发生与嵌入式逻辑分析仪的调用,程序功能完整 -Using verilog language, DDS signal generator with embedded logic analyzer called, the program features a complete
DDS
- FPGA产生DDS,未使用IP核,内含VERILOG程序-FPGA generates DDS, unused IP core, containing VERILOG program
DDS_2013_7_7_updata_past_v0.1
- DDS verilog,自己写的,验证通过!-DDS verilog made by myself,and test past!
verilog dds
- 用verilog 实现dds功能,可以实现方波,三角波等波形的输出
dds
- 在altera的FPGA上实现直接数字频率合成,即用verilog实现DDS,输出正弦波形,在modelsim软件中仿真通过,已包含所有代码和工程以及二进制流文件。-The realization of direct digital frequency synthesis in the Altera FPGA, which is implemented by Verilog DDS, the output sine wave, through the simulation in Modelsim
dds
- 采用硬件描述语言verilog进行DDS变换的实现的代码-Using hardware descr iption languages Verilog implementation of DDS converter code
DDS
- 用Verilog HDL 编写的一个最基本的DDS程序,发生正弦波-Verilog HDL prepared with a basic DDS program, the occurrence of a sine wave
DDS
- Verilog HDL实现FPGA的DDS功能,含有实验原理与代码程序-FPGA Verilog HDL realize the DDS function, principles and codes containing experimental procedures
DDS
- 基于fpga的正余弦波形发生器,Verilog代码,测试通过。-Cosine waveform generator fpga based, Verilog code, the test passes.
DDS
- 基于fpga的DDS详细设计方案 verilog语言 正弦计算器则对该相位值计算数字化正弦波幅度(芯片一般通过查表得到)。DDS芯片输出的一般是数字化的正弦波,因此还需经过高速D/A转换器和低通滤波器才能得到一个可用的模拟频率信号。-Direct Digital Synthesizer base on fpga use verilog Sine calculator to calculate the value of the digital phase sine wave amplitu
DDS
- verilog编写,使用fpga中dds手法,可以输出任意波形的发生信号。-verilog write, use the dds fpga way, you can output an arbitrary waveform signal occurs.
dds
- 在quartus软件上,采用verilog实现DDS功能。- using verilog realize DDS function On quartus software.
dds
- 这是本人在学校做的一个DDS信号发生器,频率相位可调。输入时钟50Mhz-DDS phase frequency adjustable Verilog
DDS
- Verilog实现DDS线性调频,Verilog实现DDS线性调频-Verilog implementation of DDS linear FM,Verilog implementation of DDS linear FM
DDS
- FPGA基于FPGA的DDS设计verilog程序-FPGA DDS project verilog procedure
DDS
- FPGA实现三通道DDS信号源Verliog程序-FPGA to achieve three-channel DDS signal source Verilog program
DDS(ok)
- 制作ROM正弦表并填充FPGA内部ROM,通过调用内部数据实现正弦波输出,开发环境quartusii , 语言verilog , 调试通过 , 附有modelsim调试结果。-Make ROM sine table and fill the ROM internal FPGA, by calling the internal data to achieve the sine wave output, development environment QuartusII, Language Veri
DDS
- 基于FPGA,Verilog语言编写的DDS信号发生器,可生成方波、正玄波,三角波。-Based FPGA, Verilog language DDS signal generator that generates a square wave, sine wave, triangle wave.