搜索资源列表
divider
- 用verilog实现一个被除数位8位、除数为4位的高效除法器-Verilog to achieve a dividend of 8, division by four efficient divider
frequency-divider
- 基于Quartus2和Modlesim环境下编译顺利通过的分频器源程序代码-Source code compiled Quartus2, and Modlesim environment passed the divider
divider
- 基于移位相减运算的除法器设计，完整的设计工程文件在divider文件夹下-Based on the shift subtraction divider design, complete design project file divider file folder
divider
- 时钟分频,改一下参数就能立即实现电子电路的时钟分频，用于EDA程序设计-clock divider
frequency-divider
- FA161开发板上实现分频器功能，本程序为学习FPGA入门程序，难度不大。-FA161 development board to achieve frequency divider function, the procedures for learning FPGA entry procedures, it s not difficult.
divider
- 位数可以任意修改的除法器，本人亲自测试，可以使用，效率和使用资源都是很少的-its a very good divider based on Verilog HDL
divider
- 用VHDL编写的多次分频器，带有VHDL测试平台代码-Multiple frequency divider with VHDL testbench code
divider.c
- 改良型除法器，用来模拟硬件VLSI除法器的工作步骤，是设计硬件的前序步骤-improved divider
Clock-Divider
- this verilog program, Clock Divider, can be compiled successfully by Altera and ModelSIM.
radix-4-divider
- Radix 4 Divider in VHDL
frequency-divider
- 用VERILOG 语言写的数控分频器，可能输入时钟信号实现任意整数倍的分频，-NC divider, with the words written in VERILOG HDL, can achieve any integer multiple of the input clock frequency, contains the entire project file.
Divider
- VHDL代码实现分频器设计 分频器系统时钟20万分频 上升沿触发-VHDL code Divider Design The system clock frequency divider 20 extremely Rising edge triggered
DGITAL-DIVIDER
- Digital divider details
divider
- 使用模为2N+1的计数器,让输出时钟在X-1(X在0到2N-1之间)和2N时各翻转一次,则可得到奇数分频器,但是占空比并不是50 -The use of modulo 2N+1 counter, let the output clock in the X-1 (X between 0 and 2N-1) and 2N of the turning once, then can get the odd divider, but the duty ratio is not 50
8-bit-ALU-with-a-Newton-Raphson-Divider
- 8-bit ALU with a Newton-Raphson Divider Using Verilog
DIVIDER
- M进制计数器 verilog code for divider-verilog code for divider verilog code for dividerverilog code for divider
divider
- 主要是基于VHDL的五位除法器设计，基于eda试验箱的设计。-Five main divider VHDL-based design, based eda chamber design.
float-point-divider
- 基于FPGA的单精度浮点除法器vhdl设计程序,分模块程序。-FPGA-based single-precision floating point divider vhdl design program, sub module program.
DIVIDER
- 大家好，我是复旦大学的研究生。本资源是一个基于VHDL语言的M位除以N位的除法器。其中M/N ，商M位，余数是N位的。以Moim设计验证和验证。压缩包里有除法器的源文件和testbench。可加入工程，直接测试。鄙人测试都是无错误的。愿尊驾下载后，积极评价，以便于相互交流，学习。O(∩_∩)O谢谢.2015年5月7日于芬兰，图尔库。-Hello everyone, I am a graduate student at Fudan University. This resource is base
Design-of-divider
- 除法器设计在FPGA板上的应用 除法器设计在FPGA板上的应用-The application of FPGA in design of divider class.