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16_16DIV
- 多位数除法程序，满足在单片机编程中对除法程序的需要，解决了单片机指令无除法程序的缺点，而且本程序不限制位数。-over the median divider, which meets in MCU Programming division procedures to the needs of SCM solutions division procedures directive without shortcomings, but the procedure does not limit the
subr
- VHDL 8位无符号除法器 试验报告 计算前在A和B端口输入被除数和除数，然后在Load线上送高电平，把数据存到除法计算电路内部，然后经过若干个时钟周期，计算出商和余数，并在C和D端输出。 其实现方法是，将除法器分为两个状态：等待状态与运算状态。 开始时除法器处于等待状态，在该状态，在每一时钟上升沿，采样Load信号线，若是低电平，则仍处于等待状态，如果采样到高电平，除法器读取A，B数据线上的输入数据，保存到内部寄存器a_r，b_r，置c_r为0，d_r为a_r，判断除数是否为零，若
数字系统设计相关
- 这是有关VHDL的相关源代码，有简易CPU、加法器、除法器、计数器等-This is the relevance of the VHDL source code, a simple CPU, Adder, Divider, counters, etc.
fpdiv_vhdl四位除法器
- fpdiv_vhdl四位除法器 -- DEscr iptION : Signed divider -- A (A) input width : 4 -- B (B) input width : 4 -- Q (data_out) output width : 4 -- DIV_BY_0 (DIVz) output active : high-fpdiv_vhdl four divider -- DEscr iptION : Signed divider -- A (A) in
FPGAprogram2
- 半整数分频器电路的VHDL源程序，供大家学习和讨论。 -half-integer frequency divider circuit VHDL source code for all learning and discussion.
VHDL5
- 加法器 乘法器电路 除法器电路设计 键盘扫描电路设计 显示电路-Adder multiplier circuit divider circuit design keyboard scan circuit design show circuit, etc.
clk_div_16
- 利用VHDL语言编写的一个16分频器，另外可以在程序中修改为任意2N的分频器-use VHDL prepared a 16 dividers, Also in the revision process to be arbitrary 2 N Divider
greatest-common-divider
- 一个用于计算两个数的最大公约数的逻辑算术单元-an arithmetic logic unit which is used to calculate the greatest common divider of two numbers
divider
- 用Verilog实现的除法器，通过了编译和测试，可以放心使用。-Divider implemented using Verilog, by compiling and testing, you can rest assured that use.
divider
- 输出任意频率的分频器，使用verilog语言实现-The divider wright using verilog
divider
- 分频器。可实现任意整数分频。占空比为50％，带复位端。-Frequency divider Arbitrary integer frequency can be achieved. Duty cycle is 50 , with reset terminal.
Frequency-divider
- 利用Verilog设计的在停车场情况下的模拟的分频器和计数器的代码-The use of Verilog design in the parking lot in case of analog frequency divider and counter code
NC-divider-design
- 1、 学习数控分频器的设计、分析和测试方法。 2、 了解和掌握分频电路实现的方法。 3、 掌握EDA技术的层次化设计方法。 -NC divider design
design-of-divider-
- 应用FPGA软件编写的关于除法器的小程序，适合初学者学习，很实用，而且很简单，-FPGA application software prepared by the divider small program for beginners to learn, very practical and very simple, Ha ha ha
divider
- a vhdl code for divide operation in fpga spartan6
7P(divisionymulti)
- divider and multiplier number labview
Divider
- 用Verilog HDL语言实现分频器，初学，简单(The realization of frequency divider in Verilog HDL, Elementary learning is simple)
Divider
- this is divider for verilog
frequency divider and testbench
- a frequency divider and test bench with simulation results
RPWM-matlab
- clock divider program by using VHDL