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trigger
- D触发器和JK触发器,使用emacs编写源文件,iverilog仿真通过,内有png仿真图像截屏-D flip-flop and JK flip-flop, use emacs to prepare source file, iverilog simulation adopted, within the simulation images png screenshots
jitter_eliminate
- verilog描述的实用消抖电路,采用三个D触发器和一个JK触发器。使用emacs编写源文件,iverilog仿真通过,内有png仿真图像截屏-verilog descr iption of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted