搜索资源列表
DDS-in-Verilog
- Verilog编写基于FPGA的DDS实现，内含源代码，希望对大家有所帮助。-DDS in Verilog FPGA-based implementation, including source code, we want to help.
FPGA_DDS
- FPGA中实现信号发生器,即DDS,代码简洁,精练,非常适合学习,已经经过验证.-The FPGA signal generator, or DDS, the code simple, concise, very suitable for learning, has been verified.
FPGA-DDS
- 这个是FPGA 如何实现DDS的一篇论文，希望对你有帮助 -FPGA how to implement the DDS paper, hoping to help you
DDS
- DDS信号源项目总结，本文是基于FPGA的DDS设计，采用的是SPCE061A单片机的AD9851模块-DDS signal source project summary，This article is based on the FPGA DDS design, using SPCE061A microcontroller AD9851module
dds-dingcengmokuai
- ＦＰＧＡ ＤＤＳ顶层模块 基于FPGA的dds ip核的实现，对于学习通信专业的人应该有些帮助-FPGA DDS 顶层模块
FPGA--DDS
- 文章介绍了用FPGA实现DDS的各个功能模块，实现与DDS相同的功能。-This paper introduced the method of using FPGA to instead DDS that have the same function.
dds_quicklogic-FPGA
- dds_quicklogic FPGA DDS信号源-dds_quicklogic FPGA
dds(9854)_test(sin_cos)(EP1C6)
- 通过FPGA控制DDS(AD9854)输出120M一下的双路正交信号，实现在通信和控制领域的应用。-Controlled by FPGA DDS (AD9854) output 120 m the dual orthogonal signal, realize the application in the field of communication and control.
DDS
- 基于FPGA的DDS波形发生模块，频率相位可调-Module based on FPGA DDS waveform，Adjustable frequency phase
DDS
- DDS的核心是相位累加器，相位累加器有一个累加器和相位寄存器组成，它的作用是再基准时钟源的作用下进行线性累加，当产生溢出时便完成一个周期，即DDS的一个频率周期。加载Matlab 产生的波形，通过FPGA输出DDS信号-Core DDS is the phase accumulator, a phase accumulator and phase accumulator registers, its role is to carry out a linear accumulation under
DDS
- 本代码可以实现基于FPGA的DDS系统设计，实现效果好-This code can be realized based on FPGA DDS system design, implementation effect is good
DDS
- FPGA基于FPGA的DDS设计verilog程序-FPGA DDS project verilog procedure
dds
- 已实际测试 FPGA 实现 DDS程序-FPGA DDS
DDS
- FPGA DDS的控制，可以用modelsim直接仿真，观察信号。-DDS of FPGA,able to simulate with modelsim and check the signal
bishe
- DDS(dds)
dds1
- 通过FPGA实现的，dds数字信号发生器，可产生正弦波，方波，锯齿波，三角波(DDS digital signal generator through FPGA, DDS digital signal generator, can produce sine wave, square wave, sawtooth wave, triangle wave)
src
- 使用FPGA+DAC产生DDS，可变频率(user FPGA and DAC generate DDS)
dds(1)
- 基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)
DDS波形发生器
- DDS波形生成器verilog语言书写（FPGA型号cy4以上）(DDS generate verilog)
实验二 DDS实验
- FPGA 实验程序 DDS 实验程序(FPGA PROCEDURE SHANDONG UNIVERSITY)