vhdl,十进制加减计数器，输出计数序列信号,vhdl, decimal addition and subtraction counter, the output count sequence signal

具有加、减计数以及置数报警功能的计数器，采用三个数码管显示，555产生1秒的脉冲，三块74ls192十进制计数器级联为三位数计数器。-Have add, subtract count, and buy several alarm function of counter, using three digital pipe display, 555 produce 1 second pulse, three pieces of 74 ls192 decimal counter level three

基于编码器和译码器的数码管显示，数字芯片74ls48和74ls192，还有数码管-Based on the encoder and decoder of digital tube display, digital chip 74 ls48 and 74 ls192, and digital tube

实现计数器加法、减法、清零电路。用7448、74ls192实现，可以仿真成功，适用于初学者。-Realization counter addition, subtraction, clear circuit. By 7448,74 ls192 achieve success can be simulated, for beginners.